Modelsim command to make initialization

[chico_laranja]

why modelsim undefined signal

Hi

I'm new to modelsim and VHDL files and I started in the begining: simulating simple functions.
When simulating a simple FlipFlipD I noticed that the output is undefined until my first clock cicle.
It is possible to make modelsim starting the output of the flipflops as '0' or I have to put the reset signal on the FF?

I make this question because if I have a chain of FF and a logic port after the chain I only have an output after the input run through all the FFs.

Thank's for the help.

 

[mawais]

std_logic resolve undefined modelsim

Hi I think this piece of code can help

entity my_ff is
Port (Q : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
D : out STD_LOGIC
);
end my_ff;

architecture Behavioral of my_ff is

begin
process (clk)
begin
if (clk' event and clk ='1' and reset = '0') then
D<=Q;
else
D<='0';
end if;

another option is that if you try driving the the output of one ff to the input of the other ff through signals that are initilized as zero in the begining that can also work.

like this

entity...


architecture....
signal drive1 : std_logic :='0';
signal drive2 : std_logic :='0';
.....
...
process ()---


end process
end architecture...
hope this will help

regards
Awais

 

[chico_laranja]

Re: Modelsim question

Thank's mawais

If I understand well, I have to initialize the signals.

My doubt was if the modelsim has a command that make that initialization. It should be very useful.

Thank's for the help.

Chico Laranja

 

[mawais]

Modelsim question

Yes you got my point.
No modelsim shows what is fed into through the test bench and/or design module. If the signals are not initilized modelsim rather any other simulatar will show it as an "undefined" signal. There is no way to turn the signals to some high/low level within modelsim during simulation.
Moreover its an additional alert for the designer that the dríving signals are not initilized so there can be a chance of error in the real time system (at the time of start up) due to some garbage value carried by those signals.

regards,
Awais