Mismatch contribution of input differential pair

[melkord]

Should we design our circuit so the input differential pair dominates the mismatch contribution or not? and why?

it is not explicitly mentioned here. (from Binkley's book)

 

[dick_freebird]

Well, there's two ways to get to that situation. One
is for the back end to be pristine, and one is for
the front end to be crappy. Certainly the latter is
easier. But nobody wants to pay for easy and
crappy.

Front end mismatch (Vbe / VT) is something you
can't do much about besides throw size and yield
at it, until you decide to step into either trimming
or auto-zero / zero-drift architectures. The former
demands a very low drift process (so what you
trimmed, remains so) and chopped / sampled
type corrections schemes add synchronous noise
and require some post-filtering that tamps down
bandwidth by some decades.

 

[melkord]

Front end mismatch (Vbe / VT) is something you
can't do much about besides throw size and yield
at it, until you decide to step into either trimming
or auto-zero / zero-drift architectures.

Thanks for the reply.
I am beginner here so I am still not sure what/how to decide. I understand your statement here, though.
Current-output DAC is used for trimming in my design, connected at the drain of the differential pair.
I use large diff-pair size so the input diff-pair does not dominate.
Could you check my understanding here:
Even if trimming is used, like in my case, the differential pair contribution (VTH) does not change but the differential pair contribution (delta_ID/ID) might be affected by trimming. is it right?

The former
demands a very low drift process (so what you
trimmed, remains so) and chopped / sampled
type corrections schemes add synchronous noise
and require some post-filtering that tamps down
bandwidth by some decades.

Could you explain about this part?

 

[AMS012]

Should we design our circuit so the input differential pair dominates the mismatch contribution or not? and why?

it is not explicitly mentioned here. (from Binkley's book)
View attachment 172930

I will try to give a slightly different perspective.

You are asking if the input pair dominates the mismatch in amplifiers or gain stages. You are right. The input pair is what dominates the mismatch in general. Because, the highest gain from any node to any other node in a gain stage is usually from the input to the output of the gain stage. So, all the other device mismatch, when input referred, will reduce by this gain. Whereas the input device mismatch will directly appear. This is true unless the other devices like load pair are heavily under sized.

As far as having a DAC to calibrate the mismatch goes, the vth mismatch still remains. By pumping skewed currents, you are essentially making the small signal parameters equal between the differential halves.

 

[melkord]

This is true unless the other devices like load pair are heavily under sized.

Thanks for the answer.
This was exactly what I did.
At the starting design point, the input differential pair dominates.
Then, I increased the size of input differential pair so it does not dominate mismatch.
This aligns with the discussion here.
Is this logic correct?
Apologize if this is kinda like babywalk here.

As far as having a DAC to calibrate the mismatch goes, the vth mismatch still remains. By pumping skewed currents, you are essentially making the small signal parameters equal between the differential halves.

did you mean the load pair halves? Because I checked that the DAC tries to make only the current at the load pair while the current at differential halves remains more or less the same.

 

[AMS012]

did you mean the load pair halves? Because I checked that the DAC tries to make only the current at the load pair while the current at differential halves remains more or less the same.

It depends on where you have done the common mode feedback. I guess you have done the CMFB on the load side as shown in the crude figure I drew so as to avoid any confusions on what we are talking. If that is the case, since the bottom side is a fixed current source, the extra current that the DAC pumps/sinks will flow into/out of the top PMOSs. So, this will reduce the offset but the sensitivity would be less. Instead if you do the CMFB on the NMOS side, the DAC current flows through the input pair giving higher sensitivity for correction.

Also, another point to think about is, you may need a pair of source and sink DACs so that you can pump in/out the current based on the sign of mismatch. Having only one type may not be the best for other parameters like linearity, because in the process of correction, the operating will have to change more with a single type of DAC (either sink or source DAC) compared to that with both types being used.

Another thing I would suggest is this: if you have already blown up the input device size, and still want to calibrate the offset further, then the DAC element mismatch also starts mattering more. In the process, large input devices would have hit the bandwidth, the large DAC elements further kill the bandwidth. Not sure where this gain stage is being used. If it is in some low frequency continuous time operation, you could consider techniques like chopping to reduce the offset. If it is in discrete time systems, auto zeroing could also be an option to consider (like in preamp preceding a comparator in ADCs).

 

[timof]

I would suggest to also check that the input devices are perfectly matched (their layout-dependent parameters are all the same, like WPE, LOD, etc.), and also - that their parasitics (R, C, RC, ...) are all matched as well.

IN advanced nodes, a mismatch in layout-dependent parameters, and in parasitics, may be large, and are often overlooked.