meta stable state of a design

[nishanthp68]

What is a meta-stable state?
What can be done to design
around it?

What precautions should be
taken when sending signals
between flip-flops on
different clocks?

 

[jeet_asic]

Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability.


https://www.asic-world.com/tidbits/metastablity.html