meaning of settling time?

[wael_wael]

Hi all,
could some on help me and till what is the meaning of this" The 0.05% settling time is less than 25ns at 20MHz"
it is understood settling time is lees than 25ns at 20MHz as frequency input.
but what is the meaning of 0.05%?? is it 0.05% voltt of the input signal or what?
thanx

 

[Old Nick]

If you imagine a step input (or any input to an amp), the output of the amp will take a finite time to reach its voltage, (it will oscillate a bit, and be subject to slew etc). The 25ns 0.05% rating, just says that that output will take 25ns to arrive at 0.05% of the final value.

 

[layoutmaster]

THat´s correct. Settling time % is always refered to output's final value.

 

[wael_wael]

If you imagine a step input (or any input to an amp), the output of the amp will take a finite time to reach its voltage, (it will oscillate a bit, and be subject to slew etc). The 25ns 0.05% rating, just says that that output will take 25ns to arrive at 0.05% of the final value.

thank u for the answer, but i am still confusing. how will reach the value of 0.05% in 25 ns . thats mean if the input 50mv the time needed to reach 0.05% is 25ns(that mean 25ns needed to reach 50e-3*0.05/100. is so small and can be reached easly. pls correct me if i am mistaken
regards

 

[Old Nick]

I maybe didn't explain it very well last time.

Say you put a step input ino an amp, set to unity gain for instance, then after 25ns the output will be within 0.05% of the final voltage the output will settle on at time infinity. Thus if the output voltage is to be 1V then after 25ns the o/p will be between 1.0005 and 0.9995 Volts

Added after 4 minutes:

The settling time is usually measured with a unity step, and if you look at a simulation you'll see the o/p trying to match the input, it will rise slower than the input step, then overshoot a bit and oscillate (with desreasing oscillations) until it eventually settles.

https://en.wikipedia.org/wiki/Settling_time

 

[wael_wael]

thank u so much, now is clear

 

[kumar123]

hi ,

What is the (spectre/Hspice/spice)statement to impress unit step signal ?

Regards
Kiran

 

[wael_wael]

on the other hand, for OP AMP work with supply voltage 1.8v, and max input 0.7v. how much amplitude of the unity signal for settling time test?

 

[ljy4468]

you can put 'vpulse' to source unit step signal.

 

[kumar123]

you can put 'vpulse' to source unit step signal.

meaning with Tr=Tf=0s ???

because using Tr=Tf <= 20ps i could not see rising edge ringings it is quite smooth , and slow in rise ( as slew rate is less)

so how to measure that ?

 

[Old Nick]

on the other hand, for OP AMP work with supply voltage 1.8v, and max input 0.7v. how much amplitude of the unity signal for settling time test?

Just use a smaller step. The oscillations are the dominant feature in the settling time, so it doesn't really matter that much the exact size of the step.

 

[wael_wael]

on the other hand, for OP AMP work with supply voltage 1.8v, and max input 0.7v. how much amplitude of the unity signal for settling time test?

Just use a smaller step. The oscillations are the dominant feature in the settling time, so it doesn't really matter that much the exact size of the step.

i think the size of step will affect the OTA, example, in my design when i use 50mv the settling time is 26ns, whn i use 10 mv the settling time is 70ns. so i am so confuze from that what is the best choice guys, some one help in this matter pls.
in fact if some one can help me and till if there is any book related to simulation technique ?
regards

 

[Old Nick]

You are measuring this closed loop aren't you?

https://www.analog.com/UploadedFiles/Application_Notes/466359863287538299597392756AN359.pdf

Have a read of this, and inparticular take not of the graph at the bottom right of page labelled 13-99

 

[wael_wael]

thank u so much i will read this docmnt, but the problem i cant print it . regds

 

[wael_wael]

You are measuring this closed loop aren't you?

https://www.analog.com/UploadedFiles/Application_Notes/466359863287538299597392756AN359.pdf

I Have a read of this, and inparticular take not of the graph at the bottom right of page labelled 13-99

thank u for forwarded this paper, in the paper said that, the step size should be small, how much small?. this is my question. for input 600mv how much the step size of testing settling time.
best regards