torontograd
Newbie level 2
Hi all,
I am a bit confused by how to determine the maximum number of permissible serial transistors in a logic gate in 0.18 (or technology really). Is there a limit? My thought would be that if for example, the number of series PMOS is too great, Vout of the digital gate would not rise high enough to excite the NMOS of the next gate in the logic path.
For example: is it possible to create a 5-input NAND with 0.18 technology? How about a NOR? (series PMOS instead of NMOS). How about a 6- or 7-input gate? Where is the limit?
As an experiment, I have tried testing this in Cadence, for example creating a simple chain of 3 NMOS transistors, with a small capacitor with an initial vale of 1.8V on the top of the stack. Simulation shows that the capacitor is fully discharged through the NMOS chain, as opposed to only partially discharging to 1.8V - 3 * Vth.
Thanks for any help/clarifications you can provide!
I am a bit confused by how to determine the maximum number of permissible serial transistors in a logic gate in 0.18 (or technology really). Is there a limit? My thought would be that if for example, the number of series PMOS is too great, Vout of the digital gate would not rise high enough to excite the NMOS of the next gate in the logic path.
For example: is it possible to create a 5-input NAND with 0.18 technology? How about a NOR? (series PMOS instead of NMOS). How about a 6- or 7-input gate? Where is the limit?
As an experiment, I have tried testing this in Cadence, for example creating a simple chain of 3 NMOS transistors, with a small capacitor with an initial vale of 1.8V on the top of the stack. Simulation shows that the capacitor is fully discharged through the NMOS chain, as opposed to only partially discharging to 1.8V - 3 * Vth.
Thanks for any help/clarifications you can provide!