ramdin2006
Newbie level 5
How can we check if the element of a 2D array is equal to 0 in verilog ?
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Is this possible placing the if statement inside the genvar and for look because I want to check each element of an array zero or not ? And then assign specific function for the values if its zero or non-zero element? Because when I tried the above syntax its throwing an error "A is not a constant" ? Thanks
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 module top; wire[17:0]A[1:3][1:3]; // the matrices wire[17:0]B[1:3][1:3]; wire[17:0]C[1:3][1:3]; wire[(9*18)-1:0] Abits; // bit-decomposed versions of the above wire[(9*18)-1:0] Bbits; wire[(9*18)-1:0] Cbits; genvar i,j; // set A and B with initial values generate for(i=0; i<3; i=i+1) for(j=0; j<3; j=j+1) begin assign A[i+1][j+1] = i*3 + j; assign B[i+1][j+1] = i*3 + j + 1; end endgenerate // decompose A and B, set C generate for(i=1; i<=3; i=i+1) for(j=1; j<=3; j=j+1) begin assign Abits[(((i-1)*3 + (j-1)) * 18)+17 -:18] = A[i][j]; assign Bbits[(((i-1)*3 + (j-1)) * 18)+17 -:18] = B[i][j]; assign C[i][j] = Cbits[(((i-1)*3 + (j-1)) * 18)+17 -:18]; end endgenerate initial #1 $display("%4d %4d %4d\n%4d %4d %4d\n%4d %4d %4d\n", C[1][1], C[1][2],C[1][3], C[2][1], C[2][2],C[2][3], C[3][1], C[3][2],C[3][3]); mmult3x3 U1(Abits, Bbits, Cbits); endmodule module mmult3x3 (input wire[(9*18)-1:0] AI, input wire[(9*18)-1:0] BI, output wire[(9*18)-1:0] CO); wire[17:0]A[1:3][1:3]; wire[17:0]B[1:3][1:3]; wire[17:0]C[1:3][1:3]; genvar i,j; generate for(i=1; i<=3; i=i+1) for(j=1; j<=3; j=j+1) begin assign A[i][j] = AI[(((i-1)*3 + (j-1)) * 18)+17 -:18]; assign B[i][j] = BI[(((i-1)*3 + (j-1)) * 18)+17 -:18]; assign CO[(((i-1)*3 + (j-1)) * 18)+17 -:18] = C[i][j]; end endgenerate // this is the bit that matters - everything else just works around shortcomings // in the language: generate for(i=1; i<=3; i=i+1) for(j=1; j<=3; j=j+1) assign C[i][j] = A[i][1]*B[1][j] + A[i][2]*B[2][j] + A[i][3]*B[3][j]; endgenerate endmodule
The code is as below !
I think this is the hardware approach. This code works fine.
The shortcomings aren't in the language the shortcoming is in your understanding that Verilog is a HARWARE DESCRIPTION LANGUAGE, you describe in excruciating detail the Flip-flops, the memories, the gates that make up a digital design. I suppose this is a good reason for teaching HDLs starting with structural code, it's more like hooking up ICs on a PCB than software coding. Trouble is once they introduce if statements students immediately start writing software Verilog/VHDL instead of keeping in mind they are still designing hardware.// this is the bit that matters - everything else just works around shortcomings
// in the language:
Is it possible for you write the code? Will be helpful to know how the flow works with a sample program. Considering matrix addition. Please.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 // multiply and add code that does the following: // (a * b) + c reg [31:0] mult_out, result; reg [15:0] a, b, c; always @(posedge clk) begin // pipeline stage 1, to multiply a * b mult_out <= a * b: // pipeline stage 2, to add the multiplied a * b result with c result <= mult_out + c; end