argha07
Newbie level 3
Hi ,
In LVS , i am getting stamping conflict for two different grounds in IO reported in extraction file. The owner of block(customer) has solved using by addition of CAD layer to resolve that conflict around the active area of transistor. And with that the error disappeared. Is this right way to solve this error ? What are other alternatives to solve this? Generally which CAD layer is used if you know(different for different foundaries , please mention if you know)?
My query is will not have any effect in real sillicon? Please explain. It will be great help.
Regards,
Argha
In LVS , i am getting stamping conflict for two different grounds in IO reported in extraction file. The owner of block(customer) has solved using by addition of CAD layer to resolve that conflict around the active area of transistor. And with that the error disappeared. Is this right way to solve this error ? What are other alternatives to solve this? Generally which CAD layer is used if you know(different for different foundaries , please mention if you know)?
My query is will not have any effect in real sillicon? Please explain. It will be great help.
Regards,
Argha