aarthy_maya
Junior Member level 3
hi everyone,
I have done a small circuit block, by utilizing power gating. So my top module have always ON module that tracks everything, and selectively powered modules.
The layout is clean at all basic levels (both hierarchical and flat mode, with no extraction violations/warnings either), but at top level I am getting LVS error when I do hierarchical based, whereas the error is not there during flat mode run. I am using V2012.1 of calibre integrated into Virtuoso.
Following is the error in hierarchy mode
I initially thought the error is due to not directly having power supply. But there is some module inside with gated power, that works well when I tried to debug by using LVS BOX on individual modules.
Could someone help? my experience with calibre is close to null.
I have done a small circuit block, by utilizing power gating. So my top module have always ON module that tracks everything, and selectively powered modules.
The layout is clean at all basic levels (both hierarchical and flat mode, with no extraction violations/warnings either), but at top level I am getting LVS error when I do hierarchical based, whereas the error is not there during flat mode run. I am using V2012.1 of calibre integrated into Virtuoso.
Following is the error in hierarchy mode
I initially thought the error is due to not directly having power supply. But there is some module inside with gated power, that works well when I tried to debug by using LVS BOX on individual modules.
Could someone help? my experience with calibre is close to null.