LVS ERROR IN CADENCE, HELP!

[alpineboo]

error saying:

"*WARNING* Invalid LVS run directory.
/home/**/adelab/adelabic/LVS/layout/netlist is not valid.
You must initialize the LVS run
with a valid LVS run directory before you can probe."

I have checked the si.log file.It is giving a global error regarding the cell view,

" *WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
global error:
Cannot find switch master cell for instance M1 in cellView (inverter schematic) from viewlist 'lvs schematic gate_sch cmos_sch ' in library 'expt1'.
global error:
Cannot find switch master cell for instance M0 in cellView (inverter schematic) from viewlist 'lvs schematic gate_sch cmos_sch ' in library 'expt1'.
*WARNING* invalid cell view -- 0(unknown)
si: Netlist did not complete successfully.
Comparison program did not complete. Check the log".

CAN SOMEONE HELP ME, THANKS A LOT

 

[chviswanadh]

which tool are you using for LVS

 

[tran]

You can set this envirement variable:
% setenv CDS_Netlisting_Mode Analog

 

[laglead]

maybe tool problem