LVDS Query..... need your help

[discover]

HI all

here gaurav, i m designing LVDS Tx & Rx circuit in 180nm technology, in 180nm minimum length for I/O 3.3V MOS is given as 0.36u. but someone said 2 me that u can't get better matching with minimum length, so i m going for 0.72u as length, my problem is that my common mode & differential output of LVDS have some oscillation, as shown in my figure 1.
here i am also using transmission line model with capacitance of 1.7pf & inductance of 5nH during prelayout simulation, i am using terminating resistance of 100 ohm at both end (tx & Rx side )

please help me,

1) how can i reduce the oscillation at the output waveform
2) can i also get matching if i am designing with 0.36u minimum length for I/Os
3) what more test i will have to do, so that i can confirmed whether my design is properly working or not ?
4) as i am doing prelayout simulation, how much parasitics capacitance i will put on each node so that my prelayout & postlayout simulation get nearly match ( some body told me to put 1fF cap at each node during prelayout simulations )

waiting for you help

thanks & regards
Gaurav

 

[ravi dixit]

may be reflections due to improper termination

 

[ericzhang]

How about waveform of VFB? It looks like common mode osillation.An AC analysis must be done to check the CMFB stability?

Another important issue:
The spec requests DC driver output impedance:
Minimum Typical Maximum
40ohm 90ohm 140ohm
Your schematic without nearend 100ohm termination cannot match the spec.

BR

eric
12/14

 

[jonashat]

1) how can i reduce the oscillation at the output waveform

Is this a clocked system? what does the circuit look like?

It might not be oscillations, because it is not damping, may be it is just clock feedthrough.

Try buffering the output with a couple of buffers (a diff pair with resistive loads) and that should eliminate the clock ripple on your output.

 

[malikmunish]

you need to check for loop stability

MM

 

[discover]

okay friends thnks for ur reply,can any one tell me how can i check for CMFB stability ? ( how can i connect AC source to feedback loop for AC simulation )
also can i use 0.36u minimum length for I/Os ???

I am doing prelayout simulation, how much parasitics capacitance i will put on each node so that my prelayout & postlayout simulation get nearly match ?? ( some body told me to put 1fF cap at each node during prelayout simulations )

 

[avt]

simple - open the loop - put an ac source (don't forget the dc offset) to the input of the diffpair of the common mode feedback amplifier and measure the ac gain and phase at the point between the two common mode feddback "dividing" resistors.

you should have some 60 degree phase reserve - in order to make the error small enough 40 dB should be quiet nice ...

 

[paladinzlp]

You need check the common-mode loop's stability.

 

[avt]

some remarks - the 40-140 ohms are single ended termination values in the outdated IEEE-spec - anyway I would be very happy to understand how to implement these single-ended terminations in a current.mode driver ?

The solution would be a fast (!!!) cmfb-circuit , which can eliminate the common-mode distortions which might be generated by example when the source side resistances of the current sources are not well matching ...
But this will make the cmfb quite power-hungry - wouldn't it ? - Or am I missing something ?

Anyway - I have seen also designs whcih just use a replice-circuit for biaisng the pmos and nmos-current-sources - I see no chance that these designs will ever meet the IEEE-1596 spec - but they are sold as TIA 644A compliant as far as I know - or how can one implement a 4 to 5mA-LVDS-driver that has a cmfb-circuit which has a 3dB/gbw of several 100 MHz in order to eliminate common-mode signal on the source side ? (explain this to me - please !!!)