LVDS driver question - adequate model of load ?

[Warlike]

LVDS driver question

Hi! I'm designing LVDS driver and I have a question: how simulate it correctly? =) I mean what is adequate model of load? Image in the attachment is the schematic of my testbench.

Questions:
1. Is it correct? Should I take into account transmission line, inductance, someone else or not (like now)?

2. How big is the CL?
I think it include parasitic caps, ESD, pins, PCB traces. So it is about 5pF...10pF. Does it seem right?

 

[flatulent]

Re: LVDS driver question

Cl is the input capacitances of the receiving gates. If your PC traces are 100 ohms differential, you do not need to include the transmission lines since all they do is produce a time delay.

 

[Warlike]

LVDS driver question

Thank you for explain question about transmission line.
And what about output capacitance of driver (ESD, PAD etc.)? Why it is not include in CL?

 

[flatulent]

Re: LVDS driver question

To be very accurate you will have to include the package parasitise, series inductor and shunt capacitor on all pins. The PC pad is so short that it is a negligible bump in the transmission line impedance.

 

[FvM]

Re: LVDS driver question

Interestingly, neither LVDS standards nor usual LVDS interface part datsheets are specifying load capacitances, they assume a pure resistive transmission line termination. Application literature, e. g. Nationals profound LVDS Owners Manual however says, load capacitance is considerably affecting LVDS signal quality. If you assume a load capacitance at the receiver, the transmission line can't be terminated correctly and you get multiple reflections, also depending on the driver output impedance. Gigabit and long distance transmission standards have an additional source sided termination for this reason.