Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

LVDS- data signal frequency limits

Status
Not open for further replies.

circuitking

Full Member level 5
Joined
Jan 8, 2018
Messages
291
Helped
1
Reputation
2
Reaction score
1
Trophy points
18
Activity points
2,503
Hello, what decides how much maximum can be the signal frequency in the LVDS design?
 

Last edited:

One of the relevant standards for LVDS interface is TIA PN-4584. Revision 1.2 says:
3.2 Data signaling rate The LVDS interface circuit will normally be utilized on data and timing, or control circuits. Actual maximum data signaling rate is NOT defined by this Standard. The limit is determined by the generator transition time characteristics, the media characteristics, the distance between the generator and the load, and the required signal quality.

A theoretical maximum limit is calculated at 1.923 Gbit/s, and is derived from a calculation of signal transition time at the load assuming a loss-less balanced interconnecting media. The recommended signal transition time (tr or tf) at the load should not exceed 0.5 of the unit interval to preserve signal quality. This Standard specifies that the transition time of the generator into a test load be 260 ps or slower. Therefore, with the fastest generator transition time, and a loss-less balanced interconnecting media, and applying the 0.5 restriction, yields a minimum unit interval of 520 ps or 1.923 Gbit/s theoretical maximum data signaling rate. Employing a parallel bus structure (4, 8, 16, 32, etc. - bus width) can easily extend the obtainable equivalent bit rate into the multi Gbit/s range.

A recommended maximum data signaling rate is derived from a calculation of signal transition time at the load. For example, if a cable media is selected, a maximum signal rise time degradation is assumed to be 500 ps, since cables are not loss-less (500 ps represents a typical amount of rise time distortion on 5 meters of cable media). Therefore, allowing a 500 ps degradation of the signal in the interconnecting cable yields a 760 ps (fastest) signal at the load. Therefore, with the fastest generator transition time, and a cable with only 500 ps of signal degradation (transition time), and applying the 0.5 restriction, yields a minimum unit interval of 1.520 ns or 655 Mbit/s recommended maximum data signaling rate based on this set of assumptions. Maximum data signaling rate is thus application dependant.

Generators and receivers meeting this Standard need not operate to the theoretical maximum data signaling rate. They may be designed to operate over narrower ranges that satisfy more economically specified applications, for example at lower data signaling rates. When a generator is limited to a narrower range of data signaling rates, the transition time of the generator may be slowed accordingly to limit noise generation. For example, at 100 Mbit/s the generator's transition time should be in the range of 500 ps to 3 ns (5% to 30% of the unit interval), and the signal transition time at the load should not exceed 5 ns (50% of the unit interval).

As you are posting in the Analog IC design section, the general answer is "your IC design decides about the achievable data rate".
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top