firewireblue
Newbie level 4
Suppose the power saving of design is D, which is supposedly lower than current benchmark systems. Suppose such design provides a good compromise of speed. memory and power
Suppose i added nop instruction(no instruction instruction) into the microprocessor. Since nop now provides an advantage over other systems. by survival of fittest logic, if i choose to replicate nop type power reduction scheme. not only would an copy be slow, it would also consume more power from replication of N number of nops.
Several schemes use survival of fittest logic( just psychology to choose winner), for example: Michael hsiao, sequential atpg using hadamard, Niermannn's hitec.
-suresh
Suppose i added nop instruction(no instruction instruction) into the microprocessor. Since nop now provides an advantage over other systems. by survival of fittest logic, if i choose to replicate nop type power reduction scheme. not only would an copy be slow, it would also consume more power from replication of N number of nops.
Several schemes use survival of fittest logic( just psychology to choose winner), for example: Michael hsiao, sequential atpg using hadamard, Niermannn's hitec.
-suresh