Looking for materials about optimize timing a design using Verilog code

[butxarakham.nh2008]

Hi everybody,
i have project about optimize timing the design on verilog code, but i can not find any documents of this topic. Remember that only on RTL code such as you use paralell coding style... , not by comment line such as "optimize_ timing...."....
Anyone help me?
Thanks all,

 

[kumarpals]

Re: RTL coding

**broken link removed**

 

[srinivasansreedharan]

RTL coding

Advanced ASIC Chip Synthesis - Himanshu Bhatnagar