felicia
Junior Member level 2
backend engineer resume
Hi All,
We are looking for IC Backend Enginners. The job will be based in Singapore.
Below is the job description.
If you are interested, please send your updated resume to felicia@uniconnect.com.sg. Appreciate it.
Job Description:
To prepare SoC net-list for SoC Top-level RTL for layout encompassing synthesis, Design For test insertion, formal verification check and Static Timing Analysis (STA) timing closure.
Responsibilities:
• Expert in Design for Test (DFT) to ensure the entire top-level can be implemented with 99% coverage covering both digital and analog portion using scan insertion, compression and generating, at speed test, and all kind of BIST test insertion.
• Expert Low power Synthesis, STA/timing closure and Low power Equivalent checks in SoC.
• Work with physical design engineer for the tapeout of IC.
Requirements:
• Master’s/Bachelor’s Degree in Electrical/Electronics Engineering with an emphasis in IC design.
• Minimum 3 years of experience.
• Expert knowledge of VHDL/Verilog and CAD tools (Cadence and/or Synopsys). Low Power SoC analysis flow using Common Power Format.
• Experience in SoC with millions of gate with CMOS process from 90 down to 45 and 32nm will be an added advantage.
• Experience through IC life cycle from conception, design, verification, tapeout and silicon validation.
• Able to work in a team with a strong drive to excel.
• Able to work independently on a given assignment and work hard to finish on time.
• Good written and communication skills.
Hi All,
We are looking for IC Backend Enginners. The job will be based in Singapore.
Below is the job description.
If you are interested, please send your updated resume to felicia@uniconnect.com.sg. Appreciate it.
Job Description:
To prepare SoC net-list for SoC Top-level RTL for layout encompassing synthesis, Design For test insertion, formal verification check and Static Timing Analysis (STA) timing closure.
Responsibilities:
• Expert in Design for Test (DFT) to ensure the entire top-level can be implemented with 99% coverage covering both digital and analog portion using scan insertion, compression and generating, at speed test, and all kind of BIST test insertion.
• Expert Low power Synthesis, STA/timing closure and Low power Equivalent checks in SoC.
• Work with physical design engineer for the tapeout of IC.
Requirements:
• Master’s/Bachelor’s Degree in Electrical/Electronics Engineering with an emphasis in IC design.
• Minimum 3 years of experience.
• Expert knowledge of VHDL/Verilog and CAD tools (Cadence and/or Synopsys). Low Power SoC analysis flow using Common Power Format.
• Experience in SoC with millions of gate with CMOS process from 90 down to 45 and 32nm will be an added advantage.
• Experience through IC life cycle from conception, design, verification, tapeout and silicon validation.
• Able to work in a team with a strong drive to excel.
• Able to work independently on a given assignment and work hard to finish on time.
• Good written and communication skills.
