Logical equivalence between verilog and .lib

[reddvoid]

Hi,
I was checking logical equivalence between verilog and .lib using cadence conformal
I have verilog ports

---

Code Verilog - [expand]
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module abcd  ( clk, d, o, sleep);
  input clk, d, sleep;
  `ifndef INTCNOPWR 
  inout vcc, vcc_in, vssx; 
  `endif
output o;
  `ifdef INTCNOPWR 
wire vcc, vcc_in,vssx;
'endif

---

but when I run the equivalence check I get the following error

ERROR: inout port 'vcc' of module 'abcd' is not in the terminal list on line 7 at column 9 in file abcd.v

same for vcc_in and vssx.
But I have these ports clearly defined inside ifdef and ifndef

Do anybody have any idea about this? , would be very helpfull
Thank you

 

[dpaul]

I have a question for the following statement:

I was checking logical equivalence between verilog and .lib using cadence conformal

As I know LEC is done between similar files, VHDL vs VHDL or Verilog vs Verilog.
(When you get bronze netlist is not the final one, still designer may expect changes in RTL.
Silver more or less RTL is fixed but there may be some rework done at gate level.
When you say golden netlist that means RTL and gate level changes are forzen no more changes are not allowed.)

Normally 1 file is set to be the golden/bronze/silver (better to say the old unchanged file) which is generally a netlist obtained after synth. This is generally compared against a modified RTL (to which the designer has made some changes).
In many cases 2 files can be pure RTL code or 2 files are netlists, but as I knew it the nature of the files were always similar.

I had done LEC almost 4 yrs ago, so I may be wrong, and hence asked you about the statement that clicked my mind.

 

[slutarius]

The problem look like the port list does not include vcc, vcc_in, vssx.
It should be: "module abcd ( clk, d, o, sleep, vcc, vcc_in, vssx);" instead.