engr
Member level 3
Hi all,
I am doing logic synthesis for small rtl, i created dc scripts for it and ran dc, i seen timing, none of timing paths vilolated.
Area constraints is violates, since i set max area to 0.
What are the the other things i have to look at , to conclude my synthesis netlist is correct apart from timing and area constains.
i have to look at netlist for any reason, to find out any issues in netlist
I am doing logic synthesis for small rtl, i created dc scripts for it and ran dc, i seen timing, none of timing paths vilolated.
Area constraints is violates, since i set max area to 0.
What are the the other things i have to look at , to conclude my synthesis netlist is correct apart from timing and area constains.
i have to look at netlist for any reason, to find out any issues in netlist