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Hello Dana,I dont understand the question .
I need to build a circuit that biases two CGHV1A250F RF ampliers. this is the system i described at post 39.
What else i need to say that is missing?
Thanks.
For power sequencing a processor easiest. Especially since you are dealing with
very expensive power parts you will want to initiate each step and confirm (A/D
measure) step accomplished before you go to next step.
Since voltages and currents do not seem to be critical a low end processor with
8 - 10 bit A/D should suffice.
Is this a military application, if so what country are you in ?
Hello ,Its pure educational purpose, i am from a university.
I need an analog solution type with delay lines.
A/D MCU is not an option.
COuld you please reccomend a good Analog way?
Thanks.
OK, unless your amplifiers are operated pulsed mode
this looks more like a simple supply sequencer, "human
in the loop active bias" kind of application.
A few phased array element controllers I've done, had
the drain switch and active bias control features. Any
pulsing was done by the panel, by enable signals.
Active bias amp always starts from pinched off and
drain current is the servo'd quantity, ramping from zero
after drain switch closes.
I'd bet you can find an active bias controller chip for
MMICs incapable of controlling their own Vg suitably,
pretty cheap.
Hello Tony, yes you are correct .
I just want to learn how to do sequencer .
Any practical analog reccomendations I can follow?
--- Updated ---
Hello Dana, regarding the observation you made shown below.
How do you know that Q_collector sees high impedance from the right?
What analog design logic says that?
Thanks.
Q1 & Q3||Q4 do form a Darlington emitter follower, I think mainly to present Q2 collector with high Z, eg. not load down the G stage. And
as emitter follower present low Z out.
As an example of sequencer circuits, here's 4017 IC (1-thru-10 counter) generating a quasi-sinewave. Different resistor values generate different repeating waveforms.
To design anything, you must know what function is needed for each stage. List these in your 1 page design spec, before choosing any parts or looking at any old designs. So instead of saying how does this circuit work, say what you need to do in a list or datasheet summary form. THEN SAY this is what I chose and what I tried , and here are my results and this is my problem
Learn how to design for testability (DFT) with a Design Spec and a Test Plan. So learn how to do this.
But first you need a top-down block diagram with interfaces defined. Then you define the interface signals and functions BEFORE you choose any parts or topology.
For example you need a timing diagram for power sequence up and down. For example sequencers are digital with time delays easily control like above with a clock except there it simulates a 5 level sine wave instead of controlling bias switches and power. You have the sequences defined in the MAcom spec, but not the time and V,I characteristics.. Then you need a state machine to define these states of start, ready and shutdown , stop then a trigger condition for each.
Actually you will learn as to how this was approached, and why. Since you do not seem to
have any specs, eg. delays and their values needed, and protection criteria for the RF MOSFET
then its just a guessing game, not conducive to learning. Simple analog delays can be achieved
thru use of RC networks, but thats a sloppy way of generating timing, and there is no intelligence,
eg. did the bias get turn on, oh well lets just hit it with a big pulse of drive and see if it survives.
Not good design if your goal is to become real engineer.
I have done repairs to fried transceivers who had inadequate protection, no point in learning and
repeating poor design.
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