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logic of a transistor circuit logic shown below

Y

yefj

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Hello , In the photo below, how do i know what is the analog design logic of the structure between the two arrows in the photo below?
Thanks.

1712079603732.png
 
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Hello ,I know that we enter a pulse to it, but i dont know the purpose and i ned to see the general purpose.
from A to B i guess its a level shifter ,then from B to C its a buffer,from C to D its a darlington.
What do you think is the general logic of these stage.
what is the purpose of each stage in the general logic in your opinion?
Thanks.

1712259931070.png
 
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Back in the 70's when I needed to generate two (stereo) pulses from two antenna RF sub-carriers to design a low cost system to compute Doppler Azimuth and Range, I might have started with such poor choices of transistors trying to get 1 ns accuracy but ended up with better choices of pulse shapers.

My general opinion of this design is that it is rather "sub-optimal" as we say diplomatically , but appears to provide asymmetry slew rates into say 1 nF or more pulses due to the unidirectional nature of CC emitter followers with low impedane in one polarity and the other polarity supplied by your high emitter resistance followed by two low resistors for some experimental value. One might think it was an attempt by a junior designer to make a FET driver.

Conclusion: NG from unstated source and purpose.
 
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I haven't seen a lot of really good zener fitting, the diode
model is not great for the reverse knee region even if you
have "high" and "low" breakdown params. We'd usually
measure it where we mean to run it and fit it -right there-
ignoring the irrelevant regions. But an "everything to
everybody" model is likely to have "good" and "not so good"
regions-of-fit.

Same with JFETs. Compact models are old, crusty compared
to advanced MOS and bipolar, driven by the high performance
and high dollar product development applications of those.
 
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The definitions of variables Zz and Zzk are unique to On Semi (nee Rotamola);)
yet the specify the currents at both and the impedances for the rated current and the "k" Knee voltage threshold" , sometimes called Vth and Vr and Zth, Zr.

This is called Zener voltage ( reverse) instead of Forward voltage, Vf.

This is similar to white LEDs.

Vth = 2.8 to 2.85 and Vf = Vth + If * Rs ... as a 1st approximation @ Tj=85'C is my rule of thumb.

1712280109065.png


I'm not sure if this useful or relevant, FWIW.

Tony.
 
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Hello Dana,Your essumption was correct.
I got a photos of testing this circuit.
the green signal is the signal we what to look at.
Photo with B it means the signal at point B.
Photo with C it means the signal at point C.
So it is an interter but it also amplified the signal.

I know the stage at point C is common emitter with PNP transistor.correct?
i have R19 R22 C23.
what is the important component surounding the common emitter i need to pay attention to in my simulation?

Thanks.




"R13 seems to be a trim of the pulse amplitude being fed to Q1.

So as pulse goes - into Q2 its collector goes more positive towards ground.
So it acts as an inverter."
1712317888950.png

1712317751948.png
 

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Q2 is the gain stage, and R13 does adj amplitude. Q2 has a speedup C23
to improve its switching time.

Q1 & Q3||Q4 do form a Darlington emitter follower, I think mainly to present Q2 collector with high Z, eg. not load down the G stage. And
as emitter follower present low Z out.

Not sure why Q3 and Q4 paralleled....

What is the product/instrument this is in ? What does overall system
function as ?

Regards, Dana.
 
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Hello Dana, I have tried to simulate this PNP of the data sheet in the configuration of the Q2 using the attached spice directive.
I get a very bad result,In the first stae we have 0-3.3 which is level shifted by 3.6 so the input pulse of the second stage is -3.3 to 0(approximatly)
However as you can see in the simulation and result below my pulse is not getting amplified at all,although its just like in the circuit.
Where did i go wrong?
Thanks.

1712327938560.png

1712327481378.png

--- Updated ---

UPDATE:
Hello I have updated the schematics but its amplitude of the output is 8V as shown below.
how do i make the output pulse more square?
Thanks.

1712329199779.png

--- Updated ---

UPDATE:

How does the capacitor influences the pulse? is the any theory i can read regarding it.

this circuit is a pulse shaping for power amplifier
 

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Abort this design ASAP. As I said before this design is NG (no good).

There are a dozen flaws from lack of GBW in the selected transistors, poor topology, (CC is too slow, CB is fast but low Rin), and schematic flaws with unnecessary parts.

Why do you repeatedly ignore questions about purpose like you are pretending or hiding something?

This is not Rocket Science, rather a poorly done late 60's, early 70's design attempt.

If you want a faster pulse shaper use a differential Current Model Logic or ECL chip.
 
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Abort this design ASAP. As I said before this design is NG (no good).

There are a dozen flaws from lack of GBW in the selected transistors, poor topology, (CC is too slow, CB is fast but low Rin), and schematic flaws with unnecessary parts. It behaves no better than it looks and there are basic flaws in your misunderstanding.

DO NOT parallel mismatched "active" devices like diodes and transistors. This prevents current sharing and is a "no-no"

Why do you repeatedly ignore questions about purpose like you are pretending or hiding something?

This is not Rocket Science, rather a poorly done late 60's, early 70's design attempt.

If you want a faster pulse shaper use a differential Current Model Logic or ECL chip ( which is also technology older than you)

Here's something more modern, that might be useful.


If you have source and load specs, this would be easier to offer solutions.

Again give up on this inadequate design.
 
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Hello Tony, it’s not a design task but a reverse engineering task .
I am only taking the main elements to recreate the square signals in simulation and learn from your advices to do a better job .
 
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It’s an old PCB card we have in the lab which creates pulses for power amplifier .I need to design similar circuit and it’s very helpful to have a critique from very experienced people.
I need to simulate every stage to understand the analog logic behind it .
 
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Given how sloppy the thing looks I recommend that
you start fresh, from care-abouts and modern device
options (discrete and/or integrated). Analyze from
requirements point of view, not ancient history (as
edited).

If you are bothered by storage time, look for switching
transistors, not "general purpose" and there, for least
recovery time. You could perhaps add a low-Vf Schottky
to help out by preventing hard saturation (a bad word
for BJT signal chain, a good word for MOS and a "well,
when you gotta..." for power).

Yipping out a 200ns pulse should not be hard, by various
methods. Rep rate, dimensions of variability you might want
and "cleanliness" might bear on your choice of methods.
 
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Hi,

I agree with Tony and dick_freebird.

I don't see any advantage in investing time in this outdated design.
The technology has now advanced decades.
Better devices, less effort, better signals, less development time..


Klaus
 
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Hello, Ok staring fresh :)
My task is to provide a bias voltage for two amplifiers in paralel shown below.
we have in the datasheet a sequance of operations to how properly BIAS gate and Drain.

Instead of turning switches manually ,I want to build a ANALOG circuit with delay lines which would create such pulse sequence .
What are your recommendation for the best analog implementation possible?
Thanks.

1712341738012.png
 
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