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If it's a MOS logic gate the input is voltage operated and has a very high impedance. It makes it susceptible to capacitive coupling from nearby signals and possibly also to induced voltage from magnetic coupling. This is why it is normal practise to tie unused inputs to a fixed logic level, either directly or via a pull-up or pull-down resistor. Non-MOS types usually adopt a default logic level at their inputs so although they should still be tied high or low, they are less prone to noise.
If it is related to analogue circuits or op-amps, what has been said above by betwixt still apply with the only difference that instead of connecting the input to a logic level you suitably terminate it.
I think it is in relation to capacitive coupling. If fast changing voltage or currents are in close vicinity of the High Z components, the stray capacitance between various conductors contribute to provide connectivity. The high di/dt causes induced emf that gets coupled to the input of any neighbouring device though the stray capacitance of various conductors around. If the input impedance is low, this pickup may get suppressed and contribute very little. However in the case of high input impedance circuits, the pickup (induced emf) does not die down fast and may contribute to malfunctioning.
Expanding on what ark5230 says, I didn't mean a physical capacitor like you would buy in a component store. All conductors and components have a small capacitance to each other, whether through air or a dielectric substance. When the input of a gate is very high impedance, even tiny capacitances can conduct enough signal to influence the logic level, particularly if the voltage the input floats at is near the threshold between high and low states.
Then, how will connecting this floating input to circuit ground(for low input) can solve this noise problem? Noise will be still present even if i connect it to circuit ground isn't it?
1. there is a voltage somewhere between ground and supply which is the threshold between logic low and logic high. If the gate input floats to near that voltage, even the smallest noise can push it into one or the other logic state. By tieing it low or high, the amount of noise needed to reach the threshold becomes much larger so the risk of it causing problems is very much reduced. For example, suppose your supply is 5V and the input threshold is half that, meaning anything below 2.5V is considered low and anything above it is considered high. If the gate floats to 2.5V, even a few mV of noise can make the input seem below or above the threshold and the logic level may change. If tied low, it would require more than 2.5V of noise (a huge amount) to push it over the threshold.
2. Consider the path by which the signal is coupled to the floating input. It may only take one or two pF of capacitance to conduct enough signal because the impedance at the gate is so high. By adding a resistor to pull down or up, the input impedance is made much lower and the conducted signal is made much smaller.
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