derif
Newbie level 3
Hi Friends,
I am working on AXI protocol. Among several things, a few thing are:
In case of AXI Write Txn, we have an AXI Master and an AXI Slave on other side.
Master writes the address and data on the Write Address line and Write Data on Write Data Channel. How is this Write Channel Mapped to Axi SLAVE?
similarly how is read channel in both AXI Master and Slave mapped?
Thanks
I am working on AXI protocol. Among several things, a few thing are:
In case of AXI Write Txn, we have an AXI Master and an AXI Slave on other side.
Master writes the address and data on the Write Address line and Write Data on Write Data Channel. How is this Write Channel Mapped to Axi SLAVE?
similarly how is read channel in both AXI Master and Slave mapped?
Thanks