Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

leakage current sumulation by hspice

Status
Not open for further replies.

chyau

Member level 5
Member level 5
Joined
Dec 4, 2002
Messages
87
Helped
6
Reputation
12
Reaction score
4
Trophy points
1,288
Location
Taiwan
Activity points
547
leakage

Dear All,

I need some help.please give me a hand
How to simulate leakage current by hspice ?
Could you provide me an example file
Thank you everyone.

Best Regards,
Chyau
 

hspice leakage current

Power down all the transistors of the chip. Make sure that all the PMOSes are tied to VDD and all the NMOSes to VSS. Also look into any leakage paths through resistors. Discharge all the caps to ground. Then measure the current through the power supplies. This will sum up to your leakage current.
 

hspice leakage different version

Hi,

One way to do this in any ckt is to keep it active(provide required inputs) for some time after certain time make the ckt inactive or sleepmode/standby mode(removing stimulus) measure the current through devices/elements for required period of time.

Hope this will give you a good measure.
 

hspice measure leakage

what kind of the leakage you are talking about?

how to measure the subthreshold leakage?
 

hspice leakage

I wanna know too
 

leakage current hspice

subthreshold leakage can be measured by keeping
VG=0V, Vs=0V, Vb=0V and making VD=5V (in 5v Process) and find out ID at VD=5v.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top