Latch is inferred due to RTL coding

[cafukarfoo]

Hello everyone,

I am curious why synthesis tool infer a latch when not all the possible "CASE condition" are specified.

Can anyone share their knowledge? Thanks.

 

[ljxpjpjljx]

because the circuit can't determine signal status in the other branch of case statement!

 

[cafukarfoo]

Hi ljxpjpjljx,

I am curious how the synthesis tool end up with a latch when it can determine the signal status in other branch.

Can you help to explain in more details?

Thanks.

 

[no_mad]

Hi,

When the synthesis tool cannot determine 'not define condition', it will keep the previous value.
Plus, inside ur case statement you didnt define "default:"

Thus, it will infer a latch.

example

always @(sel) // Level sensitive
begin
case (sel)
2'b00: out = I0;
2'b10: out = I1;
endcase // Here u dont define "default" value
end

In this case, what is the output value if
sel = 2'b00 --> out = I0;
Now, what is out if sel is set to 2'b11.
In simulation result, it will keep or HOLD previous value which is out = I0.

To synthesis tool, this is a latch.

Unless, u define "default: out = I1;"
Now, other than 2'b00 and 2'b10, out is by default equal to I1.

Hope my explanation is clear to u.
If u still have any doubts, pls let me know.

 

[Clunixchit]

will anyone agree with me if I take inferred latch as example to justify:

One shouldn't jump into conclusion just by looking at the combinational area, to judge the quality of a design.

If take no_mad's example,
there is a high probability that in the case of
- without default
- noncombinational area is L
- combinational area is M
- total area is L+M
- with default
- noncombinational area is 0(zero)
- combinational area is N

In most cases :
N > M but L+M > N

Just I rephrase it to
One shouldn't jump into conclusion just by looking at the combinational area, to judge the quality of a design, UNLESS THERE IS NO INFERRED LATCH.


what do you think ? Am I right ?