j-bit clock-deviding counter(vhdl,FPGA)

[starcoss]

hello everyone,

i'm a new in vhdl , i want if someone can tell what is a "j-bit clock-deviding counter" (i think that it can be j-frequency devider f/j ??? ), and if someone can give me a code in vhdl?

thank you in advance

regards,

 

[Chops211]

I will not write all the code for you, just a small snippet but from my understand it seems like you are trying to divide a clock using a counter. This would work as follows:

If you want to divide the clock by four for example you would use a signal that could count to 4 and use a comparator to drive an output clock.


process( clk )
begin
if rising_edge( clk ) then
if reset = '1' then
-- Reset the counter
counter <= (others=>'0');
elsif counter = "100" then
-- Reset the counter
counter <= (others=>'0');
else
-- Increment the counter
counter <= counter + '1';
end if;
end if;
end process;

You can either put the output clock within the process or use combinatorial logic. Up to you to decide/figure out what is necessary.

Combinatorial example:
output_clk <= '1' when counter = "100" else
'0';