Issues with the Lattice ECP5 Versa Board

[po.pe]

I'm struggling to get my design on the ECP5 Versa board running. Currently it's just for hardware verification so there's not much going on, I simply try to get an LED blinking. So this is my top entity...

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

USE work.config_package.ALL;

ENTITY top_entity IS
PORT(
SYSCLK        : IN    std_logic;
CLKOUT        : OUT   std_logic;
SOD           : OUT std_logic_vector(73 DOWNTO 0);
ds            : IN std_logic_vector(5 downto 0)
);

END ENTITY top_entity;

ARCHITECTURE rtl OF top_entity IS

SIGNAL osc, clk_160m, clk_50m, clk_i, rst_i, clken_1MHz, clken_1kHz, led : std_logic;

COMPONENT ECP5PLL IS
PORT(CLKI  : IN  std_logic;
CLKOP : OUT std_logic;
CLKOS : OUT std_logic
);
END COMPONENT ECP5PLL;

COMPONENT OSCG
GENERIC (
DIV   : Integer := 128 );
PORT (
OSC : OUT std_logic := 'X' );
END COMPONENT;

COMPONENT powerup_rst IS
GENERIC(
rst_time : IN integer := 5000     --100ms
);
PORT(
clk_i     : IN  std_logic;
rst_i     : IN  std_logic;
force_rst : IN  std_logic;
rst_o     : OUT std_logic;
rst_n_o   : OUT std_logic
);
END COMPONENT powerup_rst;

COMPONENT clockdivider_const
GENERIC(
div_value        : integer;
reset_on_disable : boolean
);
PORT(
clk_i      : IN  std_logic;
rst_i      : IN  std_logic;
enable     : IN  std_logic;
clk_out_en : OUT std_logic;
clk_out    : OUT std_logic
);
END COMPONENT clockdivider_const;

BEGIN

SOD(0)  <= led;
SOD(1)  <= '1';
SOD(2)   <= '0';
SOD(3)   <= '1';
SOD(4)   <= '0';
SOD(5)   <= '1';
SOD(6)   <= ds(0);
SOD(7)   <= '1';
SOD(9)   <= '0';
SOD(10)   <= '0';
SOD(11)   <= '0';
SOD(12)   <= '0';
SOD(13)   <= '0';
SOD(14)   <= '0';

oscillator : OSCG
GENERIC MAP (
DIV    => 32 )
PORT MAP(
OSC  => osc
);

ECP5PLL_inst : COMPONENT ECP5PLL
PORT MAP(
CLKI  => osc,
CLKOP => clk_i,
CLKOS => clk_50m
);

SOD(15)  <= clk_50m;
SOD(SOD'left downto 16)  <= (OTHERS  => '0');

-- Reset on power up
u1_powerup_rst_inst : powerup_rst
GENERIC MAP(
rst_time => 50
)
PORT MAP(
clk_i     => clk_i,
rst_i     => '0',
force_rst => '0',
rst_o     => rst_i
);

FPGA_INT <= (OTHERS => '0');
CLKOUT   <= clk_160m;

-- Clockdivider for 1MHz clock
u1_clockdivider_const_inst : clockdivider_const
GENERIC MAP(
reset_on_disable => true,
div_value        => 160
)

PORT MAP(
clk_i      => clk_i,
rst_i      => rst_i,
enable     => '1',
clk_out    => OPEN,
clk_out_en => clken_1MHz
);

-- Clockdivider for 1kHz clock
u2_clockdivider_const_inst : clockdivider_const
GENERIC MAP(
reset_on_disable => true,
div_value        => 1000
)

PORT MAP(
clk_i      => clken_1MHz,
rst_i      => rst_i,
enable     => '1',
clk_out    => OPEN,
clk_out_en => clken_1kHz
);

u3_clockdivider_const_inst : clockdivider_const
GENERIC MAP(
reset_on_disable => true,
div_value        => 1000
)

PORT MAP(
clk_i      => clk_i,
rst_i      => rst_i,
enable     => clken_1kHz,
clk_out    => led,
clk_out_en => open
);

END ARCHITECTURE rtl;

But beside of the static assignments, nothing works
so SOD(0) that should be flickering with approximately 1Hz is just statically '0' so it seems that the oscillator doesn't work. I first tried to use the external 100MHz oscillator but that also didn't work. The PLL and the OSC component seem to be infered according to the build report
OSC 1/1 100% used
PLL 1/4 25% used

Another thing that puzzles me is the following message during synthesis
WARNING - I/O Port SOD[6] 's net has no driver and is unused.

But SOD[6]'s driver should be ds[0] which is assigned to the dip switch pin H2

This is the first time I'm using Diamond and the ECP5 and I don't know if I have to include something more in my project or if the usage of the library components is wrong. It's hard to find any reference for such a design.

Does anyone have an idea where I made a mistake or has some simple project laying around that compiles for the ECP5 Versa?

 

[ads-ee]

Have you run a simulation, that would tell you a lot about what is going on.

Since this design is a bunch of components that are connected together, can't say what is the root of the problem, but I would guess it might be the sense of the reset is opposite of what you think.

I also don't quite follow the divider scheme to generate the LED, it seems less than straightforward, but I can't tell as you didn't provide the code for the divider. The last stage with the output clock of the previous stage being used as an enable seems a bit strange.

 

[po.pe]

The clockdividers are proven, we're working with these blocks for years now. It has to be an issue with the lattice specific IP blocks or the board itself, hence simulation doesn't really help much. In addition, the direct assignment from ds(0) to SOD(6) should work no matter what the rest of the code does but I get this strange message regarding "no driver". The clock enable used for the enable of the next stage is correct. Actually the second one should also use the enable of the first one, I corrected that but that was only a relict from some previous testing and didn't change the behavior.

So I don't need any GSR or PUR blocks for proper operation?

... seems like I cannot enit my initial post?

 

[po.pe]

Not sure if this is related to my problem, I tried to run a simulation in Diamond Modelsim

Seems like the oscillator works, but the other signals remain undefined. Now I wonder if propably my PLL is not simulated correctly. When checking the simulation list I found that for the OSC it recognizes a module but I don't see that for the PLL.

Shouldn't there be a EHXPLLL module inside the ECP5PLL_inst?

 

[ads-ee]

rst_i is a U so nothing in your design is getting a reset.

 

[po.pe]

That's because this is a clocked reset block, so it needs the clock as well... looks like this

ARCHITECTURE powerup_rst_behavioural OF powerup_rst IS
  SIGNAL counter : integer RANGE 0 TO (rst_time-1);
  SIGNAL reset_sig : std_logic;
BEGIN
    rst_o <= reset_sig;
    rst_n_o <= NOT(reset_sig);

  rst_gen : PROCESS(clk_i,rst_i)
  BEGIN
    -- asynchronous reset
    IF rst_i = '1' THEN
      counter <= 0;
      reset_sig <= '1';

    ELSIF rising_edge(clk_i) THEN
          IF force_rst = '1' THEN
             counter <= 0;
             reset_sig <= '1';
          ELSE
              IF counter = (rst_time-1) THEN
                 reset_sig <= '0';
              ELSE
                  reset_sig <= '1';
                  counter <= counter + 1;
              END IF;
          END IF;
    END IF;
  END PROCESS rst_gen;
 
END ARCHITECTURE powerup_rst_behavioural;

 

[barry]

This is kind of a tangled mess. You say rst_i is U because "it's a clocked reset block". But rst_i is an INPUT to that process.

 

[ads-ee]

rst_i is an asynchronous reset, so the U propagates through to all the outputs

--- Updated Jun 1, 2021 ---

Your simulation waveform starts at ~6000 ns, you need to look at the beginning of the waveform when rst_i goes U. My theory is that the powerup_reset component has an issue.

I don't understand why so many posters don't trace an X/U back through the simulation to their earliest point in time to see why it goes X/U. Once had a co-worker that didn't seem to understand that, every time they had an X or U show up in the simulation they would run back to me saying my design was broken. I'd scroll back the simulation and see they applied an X or U to an input which caused a cascade of X and U to propagate through the simulation.