Issues with refresh period and burst length in SDRAM controller design

[Eiffel.Z]

Hi friends
I am a newbie in FPGA. now I need to design the SDRAM controller to control the SDRAM w/r (Samsung K4S641632H) 64Mbit. I have some problems to ask you help me.
I refer to the datasheet, using the 50M clk
Q1: 64ms refresh period (4K cycle) . I don't know the meaning exactly. How I set the refresh time when I use the 50M working clock?
Q2: Burst length (1, 2, 4, 8 & Full page) . When I set Burst length=1, now only w/r one data on one address . but if I set burst length=8 or burst length=full page.How they worked.

Thanks
Eiffel

 

[FvM]

Re: SDRAM controller

You can reuse existing SDRAM controller examples. What's your preferred HDL?

 

[Eiffel.Z]

Re: SDRAM controller

I use the Verilog HDL
I don't know how to set the parameter of time. such as refresh time, self-refresh time, lenth and so on.

 

[FvM]

Re: SDRAM controller

Normally, refresh is carried out periodically by the SDRAM controller. I have been designing a SDRAM controller in VHDL, but I don't remember the details. I'm satisfied as long as it is operating.

I append a Verilog SDRAM controller from the Terasic DE2 board examples. There is also other SDRAM related stuff supplied with DE2, you can download the archiv from Terasic.com.tw. Unfortunately, the code is very poorly commented (as all Terasic software I've seen).

 

[cooljack]

Re: SDRAM controller

Eiffel.Z
a1: 64ms refresh period (4K cycle) .means you need send 4k refresh instruction per 64 ms. but this unnecessary if you r/w this bank with high frequency.
a2:Burst length mean how many data you will receive on data bus sequential when you send a r/w instruction to device.full page is 256 (=col addr)

hope this helpful to you!

Hi friends
I am a newbie in FPGA. now I need to design the SDRAM controller to control the SDRAM w/r (Samsung K4S641632H) 64Mbit. I have some problems to ask you help me.
I refer to the datasheet, using the 50M clk
Q1: 64ms refresh period (4K cycle) . I don't know the meaning exactly. How I set the refresh time when I use the 50M working clock?
Q2: Burst length (1, 2, 4, 8 & Full page) . When I set Burst length=1, now only w/r one data on one address . but if I set burst length=8 or burst length=full page.How they worked.

Thanks
Eiffel

 

[Eiffel.Z]

Re: SDRAM controller

Eiffel.Z
a1: 64ms refresh period (4K cycle) .means you need send 4k refresh instruction per 64 ms. but this unnecessary if you r/w this bank with high frequency.
a2:Burst length mean how many data you will receive on data bus sequential when you send a r/w instruction to device.full page is 256 (=col addr)

hope this helpful to you!

Hi friends
I am a newbie in FPGA. now I need to design the SDRAM controller to control the SDRAM w/r (Samsung K4S641632H) 64Mbit. I have some problems to ask you help me.
I refer to the datasheet, using the 50M clk
Q1: 64ms refresh period (4K cycle) . I don't know the meaning exactly. How I set the refresh time when I use the 50M working clock?
Q2: Burst length (1, 2, 4, 8 & Full page) . When I set Burst length=1, now only w/r one data on one address . but if I set burst length=8 or burst length=full page.How they worked.

Thanks
Eiffel

Hi cooljack
I have some questions wanted to consult with you. You said that send 4K instruction per 64ms, whether it have to average the time for per refresh instruction? or during the first 40ms I send 4K instruction,and rest 24ms none?
another question: if I set burst length=8, then the databus would send 8 data continuously, whether I only need designate the first address?

pls see the possible status: I set the address 0x80000, and burst length=8, then 8 data would write in 0x80000 to 0x80007, is that right?

BS
Eiffel

 

[fahadislam2006]

Re: SDRAM controller

Refresh Rate: actually SDRAM is Syncronous DRAM which means it use capacitors to store data and thats why its faster that SRAM (static RAM). So capacitors needs to be charged by time to avoid data loss so we need to apply refresh on DRAMs periodically. Mostly chips have Auto Refresh option and if you apply it, it will automatically refresh it. 64ms means that if you not refreshed your RAM within that period, your data will lost.
Burst: actually we use burst to enhance Read/Write speed from RAM and when we set burst length, it means for Read/Write that number of bits you just need to send start address of burst (you are right) so by that time to send adress for each bit reduce by burst length time.

 

[Eiffel.Z]

Re: SDRAM controller

Although I have not completely understand the truth of the SDRAM, but from your replies,I have learned more new things.Thank you.