ISE Synthesis problem - need explanations concerning 2 codes

[abionnnn]

ISE Synthesis problem

I'm missing some fundemental understanding of the synthesis process in ISE. Can you explain why the following two pieces of code generate different behaviour?

if (filter_rota && !delayed_rota) begin
	enable <= 1;
	direction <= filter_rotb;
end
else begin
	enable <= 0;
	direction <= direction;
end

enable <= filter_rota && !delayed_rota;
if (enable)
	direction <= filter_rotb;

As you may guess, the second one sends through the previous direction on edge detection.

 

[abionnnn]

ISE Synthesis problem

Obviously I've been writing too much procedural code write now, it was obvious when looking at the synthesised circuit. The first code is correct, the second is not.

Lets say that the condition filter_rota && !delayed_rota transitions to true. In the first case, the if true is traversed. In the second case, the result is written into enable, but before this is finalised, enable is tested and fails, thus not updating the direction until the next clock.

I hope this has helped.

 

[tariq786]

ISE Synthesis problem

This is what i will try.

I shall put brackets around the expression in the second code and remove non blocking statement <= statement to blocking =

See if this helps.

This has nothing to do with ISE. This has to do with verilog coding