Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Is xilinx infer arrays used in code to BRAM or DRAM?

Status
Not open for further replies.

naz56

Member level 3
Member level 3
Joined
Jun 25, 2009
Messages
54
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,698
bram xilinx

HELLO,

when arrays are used in code then XST maps it to where by default?? into Block RAM? or into Distributed RAM?a big confusion...

difference between Block RAM and Distributed RAM?
help

regards
 

it entirely depends on the size of the array and the coding style sometime.
Block ram is the dedicated ram blocks inside the fpga.
Distributed ram is basically using those Luts,SRL16 and flops in the CLBs.
block ram can operate faster than the distributed ram.
 

size of the array? explain...
 

Hi,

A small RAM (small array size) is mostly targeted to Distributed RAM. A large RAM (large array size) is mostly targeted to Block RAM.

The trade off is probably a few hundred bits but depends also on your coding style and your target device.

Devas
 

thanx to all above ppl :)
 

I noticed that relatively big register arrays do take very long synthesis time .. for me, I was synthesizing an array of 32deepX42bits and it took me 5 hours (mainly consumed in the optimization phase !!) .. any reason for that ?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top