wtr
Full Member level 5
Hello all,
I posted a similar question on xilinx forum, however I know this forum and community is much more informative and responsive.
The goal it to create a configurable gpio pad ring for an fpga design. A package file contains the information for GPIO_TC_DIR and GPIO_TC_TYPE, which are the conditions used in a generate statement to determine which io buffer is instantiated.
For full detail of the problem please see http://forums.xilinx.com/t5/Impleme...tandard-not-assignable-DRC-BIVC-1/td-p/965930
Basically in a kintex 7 I can get away with the following code, but I can't on an ultrascale (language template - doesn't show iostandard).
I'm at home now so I can't check whats available in the language template. Does anyone know of a better component I should use? (note configuring the xdc to have the values defeats the purpose of the generate & generics)
Regards,
Wes
I posted a similar question on xilinx forum, however I know this forum and community is much more informative and responsive.
The goal it to create a configurable gpio pad ring for an fpga design. A package file contains the information for GPIO_TC_DIR and GPIO_TC_TYPE, which are the conditions used in a generate statement to determine which io buffer is instantiated.
For full detail of the problem please see http://forums.xilinx.com/t5/Impleme...tandard-not-assignable-DRC-BIVC-1/td-p/965930
Basically in a kintex 7 I can get away with the following code, but I can't on an ultrascale (language template - doesn't show iostandard).
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 --vhdl08 gpio_type : If diff_type : (GPIO_TC_TYPE(I) = Differential) Generate begin gpio_dir : case GPIO_TC_DIR(I) generate when c1: input_only => begin gpio_tc_ibuf : IBUFDS generic map ( iostandard => "BLVDS_25" ) Port Map ( O => GPIO_T_IN(I), I => GPIO_T(I), IB => GPIO_C(I) ); GPIO_C_IN(I) <= '0'; end c1; --End Generate ip; elsif op : (GPIO_TC_DIR(I) = Output_Only) Generate when c2 : output_only => begin gpio_tc_obuf: OBUFDS generic map ( iostandard => "BLVDS_25" ) Port Map ( I => GPIO_T_OUT_int(I), O => GPIO_T(I), OB => GPIO_C(I) ); GPIO_T_IN(I) <= '0'; GPIO_C_IN(I) <= '0'; end c2; end generate gpio_dir; end diff_type; elsif se_type : (GPIO_TC_TYPE(I) = single_ended) generate begin gpio_t_iobuf : iobuf generic map ( iostandard => "LVCMOS25" ) port map ( i => gpio_t_out_int(i), t => gpio_t_op_enb(i), o => gpio_t_in(i), io => gpio_t(i) ); gpio_c_iobuf : iobuf generic map ( iostandard => "LVCMOS25" ) port map ( i => gpio_c_out_int(i), t => gpio_c_op_enb(i), o => gpio_c_in(i), io => gpio_c(i) ); end se_type; end generate gpio_type;
I'm at home now so I can't check whats available in the language template. Does anyone know of a better component I should use? (note configuring the xdc to have the values defeats the purpose of the generate & generics)
Regards,
Wes