Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I don't see how duty cycle should be related to tolerated clock skew, assuming standard single edge clocked designs. Minimum pulse width is link between maximum frequency and duty cycle, I think.
I'm probably using the wrong terminology, I'll try to rephrase.
An implementation inside the FPGA can work up to a frequency which I think is related to the delay with which the clock edges reach all the gates where the clock is connected, if the clock edge doesn't reach all the gated before the next clock edge then there is a problem.
For example with a 100MHz clock the period is 10ns so the clock edge must reach every gate in less than 5ns or two parts will see different clock states, with a lower or higher duty this time would be less so the resulting max frequency would also be less.
This is a correct description of clock skew in my opinion, but still don't see, how the duty cycle should affect it, as long as only one of both edge is triggering the logic.
If in the above example the 100MHz clock has a duty of 10% doesn't this reduce the available time (for the edge to arrive in all gates) from 5ns to 1ns.
From what I understand if there was a gate where the clock arrives with a delay of 2ns it would work with 50% duty but it wouldn't work with 10% duty
Whether duty is 10% or 50%, the output data from a flop is available for entire cycle(minus Ck->Q) starting at the rising edge of the clock(if pos edge flops are in use), and this data is captured by the receiving flops at the rising edge. There is nothing where the neg edge clock comes into picture. As long as the same edge is used for all the flops, duty doesn't matter.
Minimum pulse width must be met though.
It depends on the application.
in some processors the duty cycle of the clock is about 25%. In some application using both rising and folling edges of the clock for dual or quad pumping, the clock duty cycle must be 50%.
In most designs only one edge is used to latch in state change. Most ASIC's also derive clocking for several functions from the same high freq clock which often meet back up again down the line to latch in a functional result. This is where timing slew is of concern due to various propagation delays through the circuits and IC layout. Clock jitter can also eat up timing margin as the jitter propagates down various circuit paths.
Sometimes both rising and falling edges of the clock are used for a given function. An example is syncronous serial data bus (SPI bus) where data is presented by transmit side on leading edge and latched in by receiving end on the falling edge.
Even when using a single edge there is a minimum setup time where the clock must stay high or low for a minimum period after the edge which, in effect, puts a minimum to the clocking duty cycle.
Whether duty is 10% or 50%, the output data from a flop is available for entire cycle(minus Ck->Q) starting at the rising edge of the clock(if pos edge flops are in use), and this data is captured by the receiving flops at the rising edge. There is nothing where the neg edge clock comes into picture. As long as the same edge is used for all the flops, duty doesn't matter.
Minimum pulse width must be met though.
Hi,
For a clock signal the minimum clock low period,minimum clock high period and rise and fall times are specified. The duration of one cyle is the sum of all the above. Generaly clok high and clock low minimum periods are more or less equal. Hence at 50 % duty cycle maximum frequency of operation is attained.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
