meeyaw
Junior Member level 3
Hi,
I have question that currently tricks me. Here is diagram for the reference for my questions
gpwr is a power gated supply when PWRPMOS is enabled.
1.In my current SPICE run, the bounce on the gnd is higher that drop in the pwr rail. Is that possible?
2. Based on the diagram, i expect that worst IR drop (ground bounce) be found on rightmost buffer (which is 1x), but it appears that the last 10x had the worst ground bounce. Is the size of the buffer plays a role on IR analysis?
Note: buffers are 100MHz drivers
Thanks for any replies. Just need to hear someone to clarify my confusion.
Thanks,
meeyaw
I have question that currently tricks me. Here is diagram for the reference for my questions
gpwr is a power gated supply when PWRPMOS is enabled.
1.In my current SPICE run, the bounce on the gnd is higher that drop in the pwr rail. Is that possible?
2. Based on the diagram, i expect that worst IR drop (ground bounce) be found on rightmost buffer (which is 1x), but it appears that the last 10x had the worst ground bounce. Is the size of the buffer plays a role on IR analysis?
Note: buffers are 100MHz drivers
Thanks for any replies. Just need to hear someone to clarify my confusion.
Thanks,
meeyaw