ipcoregen in spartan 3e fpga

[manoranjan sb]

hi i want to store the output of my verilog program in a bram. how can i use the bram for storing output.
for giving inputs i used bram using ipcoregen wizard. pls help for storing output.

 

[kirill]

Hi
What is the exact obstacle in using block ram to store data?

 

[manoranjan sb]

i dont know how to write the output result of my program which are binary values in the bram. for taking inputs i used coregen wizard. but for storing outputs, is there any technique available. can you write any example for this. pls

 

[kirill]

This is example of block RAM from ISE coding templates :


parameter RAM_WIDTH = <ram_width>;
parameter RAM_ADDR_BITS = <ram_addr_bits>;

(* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
reg [RAM_WIDTH-1:0] <ram_name> [(2**RAM_ADDR_BITS)-1:0];
reg [RAM_WIDTH-1:0] <output_data>;

<reg_or_wire> [RAM_ADDR_BITS-1:0] <read_address>, <write_address>;
<reg_or_wire> [RAM_WIDTH-1:0] <input_data>;

always @(posedge <clock>) begin
if (<write_enable>)
<ram_name>[<write_address>] <= <input_data>;
<output_data> <= <ram_name>[<read_address>];
end;

So input_data is your output result of your program.
If later you are going to use your stored data in random order, use RAM type above. If you are going to use your data in sequential order, try to use FIFO(xilinx offer core in CoreGen), it is more simple in usage.