IO pads testing for esd protection

[raj_shekar]

I am new to esd protection.
how do u test the IO pads for esd protection
please guide me

 

[ckshivaram]

check this last attachment in the link
https://www.edaboard.com/threads/139491/

---------- Post added at 15:30 ---------- Previous post was at 15:28 ----------

some good links
ScienceDirect - Solid-State Electronics : ESD protection design for I/O libraries in advanced CMOS technologies
**broken link removed**

 

[raj_shekar]

i dont have access to science direct.
I have iopads availble in the technology library. i have to test them for esd protection, so i need to know what are the tests should be performed ?

 

[mikersia]

test procedures are defined by international standards,- see documents of JEDEC, IEC. Exist a few types of ESD tests: HBM (Human Body Model), CDM (Charge Device Model), MM (Machine Model). For each exist special test equipment. Main way to make ESD tests - to contact with test house, offering such service.

 

[raj_shekar]

I have to work on the shematics of IO pads which also has esd protection.
so i have to test the esd protection, what is the way to do it

 

[Teddy]

What you are saying is that you have to design ESD protection AND test it in lab?
If you are supposed to test it you probably have ESD test setup in house - then ask somebody who did it before or read manual.
If you do not have the tester you have to go outside and ask for service - so you will not do it by yourself.
To design ESD protection structure - stick with the strusctures which are described in your design manual. If you are new to this it is the safest way to go.
In general for testing you keep pins floating except ie GND and test pin. Then you provide ESD voltage pulse and see if there is any DC or AC difference on tested pin. And you go through all the different pin combinations.... As mentioned above go to search JEDEC spec. And google - there is tons of stuff about it.

 

[leo_o2]

For lab test, pls find expert company for ESD test if you are not familiar with it.
For design phase, ESD can't be accurately simulated by now.
Just follow basic guide lines for design.

 

[palmeiras]

raj_shekar,

The simulation of ESD event is possible IF you technology design kit allows it. It needs the proper models for the diode/MOS devices…. For instance: IBM technology supports this kind of simulation.
In addition, there are simple configurations that you can use to simulate this event – when the design kit allows it.
For example, a 100 pf capacitor (initial voltage of 2kV) in series with a 1.5 k resistor can be used to simulate HBM events.

Regards.

 

[dick_freebird]

You can "forward design" ESD protection -if- you have realistic models and
those models express the entirety of the current loop, every pin, every
combination.

You got that?

If it's a foundry PDK that came by magic, probably not.

Which puts you in the position of either blind luck, or getting better.

You can make your own transmission line pulser and test devices for
very little money; surplus Variac, a 100' roll of coaxial cable, a mercury
relay and a pushbutton switch. Then you can hook up your 'scope
and take the data and fit models to that.

But I bet you were looking for an Easy Internet Answer. Sorry.

 

[leo_o2]

Accurate ESD simulation should include thermal effect and dynamic effect.
It is very hard to do.