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Inverter Design Issue

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anishsingh

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Hi ,
i am supposed to do a full custom design a 1 Mhz cmos ring oscillator consisting of 5 stages of inverters with CL = 10pf. The delay of each stage comes out to be 0.1 usec..
i am using 180 nm umc cmos technology with 3 volts supply.How do I find the W/L values of each transistor? I know the W Of Pmos = 2 * W of Nmos ..

Kindly show me a helpful link if possible !
 

Some more : Do I need to give some kind of transient stimulus in cadence virtuoso to get oscillator into running.. Everything is coming in saturation and the voltage is settling to a fixed value in trans response

Plzz Help !!
 

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