Interview Question: Delaying Negative Edge Of Input By Two Cycles

[spartanthewarrior]

Hi All,

There is a interview question

You have a flip flop with clock and signal (A) as an input.

At output we have to delay (negedge) of signal (A) by (2) clock cycles.

Assume: At input signal (A) is high for (3) clock cycles.

 

[ebuddy]

You don't have to do anything special, just put another FF after the first one, and it should do.

 

[somg]

Hmm.. Only neg-edge huh.. How about this. The flop has a clock-gating cell in front of it. When A is HIGH, clock-gate always active. When A is LOW, clock-gate ENABLE delayed by 2 clock-cycles.
Do you think this will work?

 

[kumar_eee]

just delay the data or capture the data on every 2nd clock pulse?