Interface on board ADC to Spartan 3E

[deepanwita@gmail.com]

sir,

I am trying to interface with the ADC on my Spartan 3E starter board.

i canot see the o/p in the led. i give the i/p from jp9(on board spatarn 3e)......pls sir help me to find out the error or problem my code............or process of to see the o/p of the adc...below i paste my code....its urgent hlep me............


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity AD is
Port ( SPI_SCK : out STD_LOGIC;
AD_CONV : out STD_LOGIC;
SPI_MISO : in STD_LOGIC;
SPI_MOSI : out STD_LOGIC;
AMP_CS : out STD_LOGIC;
AMP_SHDN : out STD_LOGIC;
AMP_DOUT : in STD_LOGIC;
mclk: in STD_LOGIC;
amplitude1: out STD_LOGIC_VECTOR(13 downto 0);
amplitude2: out STD_LOGIC_VECTOR(13 downto 0);
LED : out std_logic_vector(7 downto 0);
trigger : out std_logic);
end AD;
architecture Behavioral of AD is
type state_type is (idle, set_amp, read_adc);
signal state : state_type := set_amp;
type state_type_clock is (clock_on, clock_off);
signal state_clock : state_type_clock := clock_off;
signal cnt : integer range 0 to 40 := 0;
signal clk_sample : STD_LOGIC := '0';
signal gain_set : STD_LOGIC := '0';
signal amplitude1_buffer : STD_LOGIC_VECTOR(13 downto 0);
signal amplitude1_buffer_n : STD_LOGIC_VECTOR(13 downto 0);
signal amplitude2_buffer : STD_LOGIC_VECTOR(13 downto 0);
signal gain1 : STD_LOGIC_VECTOR(3 downto 0) := "0001";
signal gain2 : STD_LOGIC_VECTOR(3 downto 0) := "0001";
signal risingedge : std_logic := '1';
signal counter : integer range 0 to 34;
begin

-- 1.5MHz clock
clock_divider : process (mclk)
begin
if(rising_edge(mclk)) then
if(counter = 33) then
risingedge <= risingedge xor '1';
clk_sample <= clk_sample xor '1';
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;

sclk_clock : process(mclk)
begin
if(rising_edge(mclk)) then
case state_clock is
when clock_on =>
SPI_SCK <= clk_sample;
when clock_off =>
SPI_SCK <= '0';
end case;



end if;
end process;

main : process (mclk)
begin
if(rising_edge(mclk)) then
if(counter = 33 and risingedge = '1') then
-- Set gain at -1
case state is
when set_amp =>
AMP_CS <= '0';
AMP_SHDN <= '0';
if (cnt < 4) then
SPI_MOSI <= gain2(3 - cnt);
cnt <= cnt + 1;
state <= set_amp;
state_clock <= clock_on;
elsif (cnt > 3 and cnt < 8) then
SPI_MOSI <= gain1(7 - cnt);
cnt <= cnt + 1;
state <= set_amp;
elsif (cnt = 8) then
cnt <= 0;
AMP_CS <= '1';
state <= idle;
end if;

when idle =>
-- 13ns delay
if (cnt < 2) then
AD_CONV <= '1';
cnt <= cnt + 1;
state <= idle;
elsif (cnt = 2) then
AD_CONV <= '0';
cnt <= 0;
state <= read_adc;
trigger <= '0';
end if;

when read_adc =>
if (cnt < 2) then
cnt <= cnt + 1;
state <= read_adc;
state_clock <= clock_on;
elsif (cnt > 1 and cnt < 16) then
amplitude1_buffer(15 - cnt) <= SPI_MISO;
cnt <= cnt + 1;
state <= read_adc;
elsif (cnt > 15 and cnt < 18) then
cnt <= cnt + 1;
state <= read_adc;
elsif (cnt > 17 and cnt < 32) then
amplitude2_buffer(31 - cnt) <= SPI_MISO;
cnt <= cnt + 1;
state <= read_adc;
elsif (cnt > 31 and cnt < 34) then
cnt <= cnt + 1;
state <= read_adc;
elsif (cnt = 34) then
cnt <= 0;

if(amplitude1_buffer(12) = '1') then
amplitude1_buffer_n(13) <= amplitude1_buffer(13);
amplitude1_buffer_n(12) <= amplitude1_buffer(12);
amplitude1_buffer_n(11) <= not(amplitude1_buffer(11));
amplitude1_buffer_n(10) <= not(amplitude1_buffer(10));
amplitude1_buffer_n(9) <= not(amplitude1_buffer(9));
amplitude1_buffer_n(8) <= not(amplitude1_buffer(8));
amplitude1_buffer_n(7) <= not(amplitude1_buffer(7));
amplitude1_buffer_n(6) <= not(amplitude1_buffer(6));
amplitude1_buffer_n(5) <= not(amplitude1_buffer(5));
amplitude1_buffer_n(4) <= not(amplitude1_buffer(4));
amplitude1_buffer_n(3) <= not(amplitude1_buffer(3));
amplitude1_buffer_n(2) <= not(amplitude1_buffer(2));
amplitude1_buffer_n(1) <= not(amplitude1_buffer(1));
amplitude1_buffer_n(0) <= not(amplitude1_buffer(0));
amplitude1<=amplitude1_buffer_n;
LED(0) <= amplitude1_buffer(4);
LED(1) <= amplitude1_buffer_n(5);
LED(2) <= amplitude1_buffer_n(6);
LED(3) <= amplitude1_buffer_n(7);
LED(4) <= amplitude1_buffer_n(8);
LED(5) <= amplitude1_buffer_n(9);
LED(6) <= amplitude1_buffer_n(10);
LED(7) <= amplitude1_buffer_n(11);
else
amplitude1<=amplitude1_buffer;
amplitude2<=amplitude2_buffer;
LED(0) <= amplitude1_buffer(4);
LED(1) <= amplitude1_buffer(5);
LED(2) <= amplitude1_buffer(6);
LED(3) <= amplitude1_buffer(7);
LED(4) <= amplitude1_buffer(8);
LED(5) <= amplitude1_buffer(9);
LED(6) <= amplitude1_buffer(10);
LED(7) <= amplitude1_buffer(11);
end if;
state_clock <= clock_off;
state <= idle;
trigger <= '1';
end if;
end case;
end if;
end if;
end process;
end Behavioral;

 

[mrflibble]

Can you be more specific? "Help help it doesn't work! It is urgent!!!" usually means your homework is due tomorrow.

So if you want help with your homework you really have to be more specific about the problem. What works? What doesn't? What did you try? Testbench results, screenshots, specifics, etc. People around here generally are pretty helpful, but you'll have to provide a bit more than "doesn't work".

 

[deepanwita@gmail.com]

sir,
i post my code. i download this code in spartan 3e. but when i try to see the output in led or through ChipScope Pro 11.1 Software,i cant see the output.
is there any error in my code? i cant find the error of my code. pls send me the procedure of checking the output of the adc.if the code is wrong then give me vhdl code of the spartan 3e adc interface and ucf file. plz help me .......................its urgent...............

 

[mrflibble]

If you zip your complete ISE project directory and attach it I'll take a look at it.

 

[mrflibble]

Given your post count + frequency of urgent @_@ messages, that should probably be ... look at it in a week or so.

 

[deepanwita@gmail.com]

If you zip your complete ISE project directory and attach it I'll take a look at it.

sir,
i upload my complete xilinx ise 11.1 project .take it pls. pls help me
thanking you

 

[mrflibble]

That is no ISE project. That is the code from your first post cut & pasted into a word document.

Same time next week for this urgent matter?

 

[deepanwita@gmail.com]

sir,
i upload my complete xilinx ise 11.1 project .take it pls. pls help me
thanking you

sir,
i upload my complete xilinx ise 11.1 project .take it pls. also tell me the procedure to check the out put of the adc in led or through ChipScope Pro 11.1 Software after burn the program in spartan 3e kit board................and give the vhdl code of the spartan 3e adc interfacingplsif it is wrong........ help me

thanking you

 

[mrflibble]

It synthesizes well enough. Mapping throws plenty of errors because your UCF file is not the correct one for the specific chip you selected. So either you are using the wrong UCF, or you have selected the wrong chip/package. You tell me, it's your board. So you may want to put some effort into getting the correct ucf for your board / selecting the correct chip/package.