flote21
Advanced Member level 1
Hello guys!
i am using a sensor which is providind data at 40MHz and after doing a data processing of this data. And my ETH IP is working at 80 MHz. I am working with Altera Cyclone IV FPGA and I would like to know if the only posibility to adapt this speed is using a DCFIFIO with a input clock of 40MHZ and a output clock of 80MHz. Or maybe there is another solution much more easier?
Thanks!
i am using a sensor which is providind data at 40MHz and after doing a data processing of this data. And my ETH IP is working at 80 MHz. I am working with Altera Cyclone IV FPGA and I would like to know if the only posibility to adapt this speed is using a DCFIFIO with a input clock of 40MHZ and a output clock of 80MHz. Or maybe there is another solution much more easier?
Thanks!