[SOLVED] [innovus] pad location is empty

[Jordon]

Hi, when i try to run rail analysis, it need a XY file, but i cannot create a XY file as tutorials, tap 'create', the Pad location list is empty, what is the possible reason? in thr tutorial, the pad location list has two items:VDD and VSS, but mine is not.
Thank you.

 

[ThisIsNotSam]

do you have pads on your layout? The screenshot on the background appears to be a block design, not a top level chip design.

 

[Jordon]

do you have pads on your layout? The screenshot on the background appears to be a block design, not a top level chip design.

No pads, i want this module as a blackbox for after top design, so i donot place io pads, do you mean the module need io pads to generate XY files? Is there some methods for this module to rail analysis without XY files? I have tried def pins menu among 'DEF pins, pad file, XY file, Boundry file', but it still dont works.

 

[ThisIsNotSam]

What happens when you try DEF pins?

 

[Jordon]

What happens when you try DEF pins?

I dont have DEF file also, So if i tap 'DEF pin' and 'create', it looks the same. And if i only select 'DEF pin' without ''create'', and add the VDD by this way, it run with some error message ,here is the log.

 

[Jordon]

I dont have DEF file also, So if i tap 'DEF pin' and 'create', it looks the same. And if i only select 'DEF pin' without ''create'', and add the VDD by this way, it run with some error message ,here is the log.

-------------------------------------------------------------------------------------------------------------


Started Rail Analysis at 17:39:30 01/05/2023


Multi-CPU Configuration:
#CPU: 1
Mode: local
Host: ic2

Analyze Rail Settings:
Temp directory: /tmp/innovus_temp_122954_ic2_lvzd_KtkZyQ
Output directory: ./run1
Run directory: ./run1/VDD_25C_avg_3



Running R extraction for /tmp/innovus_temp_122954_ic2_lvzd_KtkZyQ/eps_out_122954.def.gz ...

Invoking: "/opt/eda/cadence/INNOVUS201/tools.lnx86/ssvtools/bin/64bit/voltus_scheduler -nt 1 -usecellid -session_file ./work/sfe.session -prev_session_file ./work/sfe.session.prev -cmd ./work/voltus_scheduler.cmd" ...
Extraction option setup as:
setenv gray_data NONE
setenv enable_cluster_overhang_via false
setenv enable_dfm_mask_conflict_shape false
Begin Preparing Data for Parasitic Extraction
Extracting following DFM effects:
MetalFill : n/a
WEE Effects : n/a
Erosion Effects : n/a
T/B Enlargements : ON
R(w) Effects : ON
R(w,s) Effects : n/a
R(sw,st) Effects : n/a
TC(w) Effects : n/a
Some effects indicate n/a because of non-availability of relevant input data (or) requested to be off.
Ended Preparing Data for Parasitic Extraction: (cpu=0:00:00, real=0:00:00, mem(process/total/peak)=31.59MB/5182.64MB/2693.64MB)

Invoking: "/opt/eda/cadence/INNOVUS201/tools.lnx86/ssvtools/bin/64bit/voltus_scheduler -skip_prep -nt 1 -usecellid -session_file ./work/sfe.session -prev_session_file ./work/sfe.session.prev -cmd ./work/voltus_scheduler.cmd -zx /opt/eda/cadence/INNOVUS201/tools.lnx86/ssvtools/bin/64bit/voltus_extractor" ...
Extraction option setup as:
setenv gray_data NONE
setenv enable_cluster_overhang_via false
setenv enable_dfm_mask_conflict_shape false
Begin Parasitic Extraction
Extracting Progress:
0% at 17:39:32 01/05/2023
100% at 17:39:37 01/05/2023
Ended Parasitic Extraction: (cpu=0:00:00, real=0:00:05, mem(process/total/peak)=18.43MB/4385.41MB/2693.64MB)

Invoking: "/opt/eda/cadence/INNOVUS201/tools.lnx86/ssvtools/bin/64bit/voltus_rail_smg -cmd ./run1/voltus_rail_smg.VDD.cmd -l ./run1/voltus_rail_smg.VDD.log" ...
Begin Merging power grid
Tech reference temperature: 25
Target temperature: 25

Grid Statistics of Net VDD:
- NODE
Total node: 137
Top Level grid node: 137
Top level interface node: 72
Missing interface node: 0
Cell internal node: 0
- ELEM
Total element: 143
Top Level grid element: 143
Cell internal element: 0
- INST
Instance logically connected: 72
Tech: 72
StdCell: 0
Macro:
Early: 0
IR: 0
EM: 0
Current Region: 0
Dropped instance due to missing/incomplete cell library: 0
- TAP
Total tap: 72

Ended Merging power grid: (cpu=0:00:00, real=0:00:00, mem(process/total/peak)=36.83MB/4521.60MB/2693.64MB)

Begin Preparing Data for Rail Analysis
Loading DEF pins
Power Pin Location File: /home/lvzd/lvzd_eFPGA/ForBlackBox_TSMC18/N_term_single/Innovus/run1/VDD_25C_avg_3/VDD_vsrcs.rpt
** WARN: (VOLTUS_RAIL-2040): The variable "use_toplevel_pins" is set to true but no DEF pin is found.
** ERROR: (VOLTUS_RAIL-1261): Rail analysis cannot continue because there are no voltage sources annotated for net "VDD".
Exiting Rail analysis due to net without vsrc.
1 error was found while processing the file /tmp/innovus_temp_122954_ic2_lvzd_KtkZyQ/voltus_rail_122954.cmd

Rail Analysis Statistics:
Warning messages: 1
Error messages: 1

Rail Analysis is unsuccessful due to errors.

Finished Rail Analysis at 17:39:37 01/05/2023 (cpu=0:00:02, real=0:00:07, peak mem=2693.64MB)
Current Innovus resource usage: (total cpu=0:39:03, real=9:38:25, mem=2154.70MB)
voltus_rail exited unsuccessfully.

 

[rca]

A DEF file, will provide position and metal used to place the top pin of your design, nothing related to the PAD instance.

In your case you can point the rail analysis to any point on the metal (ring or stripe) closer to the supply driver.

 

[Jordon]

A DEF file, will provide position and metal used to place the top pin of your design, nothing related to the PAD instance.

In your case you can point the rail analysis to any point on the metal (ring or stripe) closer to the supply driver.

Ok, many thanks