sajjad.hussain
Junior Member level 1
I synthesized Leon3 with two different options:
It produce a single top level verlig module with all the module merged inside. During synthesis there are some uninitialized FF which cause 'x' propagation and results in incomplete annotation while doing power estimation. For that I can initialize all the FF in verilog file by searching all FF using Linux 'sed', before the modelsim simulation starts, then producing SAIF, then power estimation is done with 100% annotation.
But
It preserves the original design hierarchy in terms of verilog modules, and save synthesized netlist in a verilog file. Now there are many modules, before modelsim simulation how to initialize all the FF in different modules?
Please guide.
Best Regards, Sajjad
- flatten-all & auto-ungroup:
It produce a single top level verlig module with all the module merged inside. During synthesis there are some uninitialized FF which cause 'x' propagation and results in incomplete annotation while doing power estimation. For that I can initialize all the FF in verilog file by searching all FF using Linux 'sed', before the modelsim simulation starts, then producing SAIF, then power estimation is done with 100% annotation.
But
- no-auto-ungroup
It preserves the original design hierarchy in terms of verilog modules, and save synthesized netlist in a verilog file. Now there are many modules, before modelsim simulation how to initialize all the FF in different modules?
Please guide.
Best Regards, Sajjad
Last edited by a moderator: