Information about designing 12 bits R2R DAC

[jeremy_zhu]

i want to design a 8 bits SAR ADC, and i have designed one by weighted capacitor. i would like to decrease the power and area. i think i should choose the R-C weighted ADC whose msb is realized by cap for small area by using less caps. but i don't know how to decide the related bits, 5(cap) +3(res) or in reverse. and what's the difference between sar logic of pure cap and the desired one.
any comments or suggestions?

2nd question: design of a 12bits R2R DAC. res matching ,any other emphasis or attentions? some related docs or papers are also welcomed.

 

[evi]

adc using r-2r

2nd question: design of a 12bits R2R DAC. res matching ,any other emphasis or attentions? some related docs or papers are also welcomed.

It's very hard to acheve 12 bit accuracy matching with R2R. You will have to use thermometer coded ladder for MSBs, but even with that the area has to be very large in order to achieve the required matching. Also pay attention to resistors nonlinearity, your resistors may not be linear enough for 12 bit accuracy, but this depends on the process you use. Other concern - comparator offset. You will definitely need auto-zeroing, but even auto zeroing has some residual offset due to charge injection which is hard to simulate accurately. Also pay attention to noise, including kT/C of the autozeroing caps. If the speed requirement is not too stringent you can use correlation double sampling, it will remove all offsets and cancel 1/f noise below the sampling frequency, so that you may even get away without autozeroing the comparator. One more concern - use PMOS for the input pair of the comparator becaue NMOS has charge trapping effect. The charge trapping occurs in NMOS after applying a large differential signal to the input pair, which causes a few mV offset with time constant of a few ms. In SAR the input of the comparator is usually exposed to large differential voltages, so charge trapping is a concern.