Incoming netlist checking

[urslen]

I want to get some information on the following :

I want to analyze the incoming netlist (V/VHD/EDF) from the front end team and find out the possible difficulties in the back end.

(mainly the problem that will arise like
1. open port from a macro,
2. assigning a=~b;
3. directly using 1'b0 or 1'b1 which will have direct connection with the gate to the power stripes.)

So I would like some more information on
-what are all the difficulties can be ofaced in a Physical design because of the bad coding style mainly.
-how to get those information by seeing the netlist.

Some advise and information is very much needed

 

[abhishek_elec]

If you are also working on timing closure, ask the front-end guy if there are any clock loops. If they are present, give them explicitly in Astro. Front-end tool automatically breaks them but backend tools are not smart enough.
If you dont break these loops explicitly in tool, you may get many problems afterwards.

 

[urslen]

Thanks abhishek,

....and I want to add some more information that I was planning to write a script to find out some common problem by seeing (input to the script is netlist) the netlist that may arise during the Physical Design..........

shortly it's a netlist screener

 

[abhishek_elec]

Keep posting on this thread what mor e checks u r planning to put on ur incoming netlist .... it will be helpful for me too...

 

[urslen]

yah I will put more points on this.It'll take some more time I guess... but still waiting for somebody to give me more suggestion.

 

[patrickli]

I feel (2), (3) has no prolem.
astro can do with "assign" now.
In fact, the important thing is you need check sdc with PT firstly.
see whether sdc is not reasoniable.

 

[sakshi gupta]

I want to get some information on the following :

I want to analyze the incoming netlist (V/VHD/EDF) from the front end team and find out the possible difficulties in the back end.

(mainly the problem that will arise like
1. open port from a macro,
2. assigning a=~b;
3. directly using 1'b0 or 1'b1 which will have direct connection with the gate to the power stripes.)

So I would like some more information on
-what are all the difficulties can be ofaced in a Physical design because of the bad coding style mainly.
-how to get those information by seeing the netlist.

Some advise and information is very much needed

Hi usrlen,

Did you get some document that lists the scenarios in Netlist that will cause issues in backend ?

Thanks
Sakshi

 

[yx.yang]

I want to get some information on the following :

I want to analyze the incoming netlist (V/VHD/EDF) from the front end team and find out the possible difficulties in the back end.

(mainly the problem that will arise like
1. open port from a macro,
2. assigning a=~b;
3. directly using 1'b0 or 1'b1 which will have direct connection with the gate to the power stripes.)

So I would like some more information on
-what are all the difficulties can be ofaced in a Physical design because of the bad coding style mainly.
-how to get those information by seeing the netlist.

Some advise and information is very much needed

Hi, urslen:
I think 2) and 3) can be checked by "vi", using search will be ok.
For 1), I think it can be done by PT. The steps maybe:
a): read the design in and link the design up
b): get the input pins of each cells
c): use "all_fanin" to check the fanin of each input pins. And check whether there is any fanin for a given pin.

For step b) and c) there may not dedicate PT command, you need write a little TCL script to finish that (combine come PT commands together).

I don't know what you want to check next.

Thanks.

 

[kumar_eee]

In Back-end, I check the following checks in the incoming netlist.
1) Check whether all the cells are available in the library.
2) Check for the ports unconnected.
3) Check for the .lib models availability for all the cells.
4) Check the timing with Zero Load Model & get back to the designer if you find any worst violations.