Inaccuracy between EM Sim and fabrication

[Orey]

Hello all,

I do fabricate rectifier using SMD diode and capacitor for a project and I found a lot of inaccuracy between simulation and fabrication. For example, I do have a shift as visible here (blue is experimental):

https://imgur.com/PkwGQmr

I tried to simplify my circuit to see if it's coming from my substrate definition or components and find similar results when I look on the S11 but not on the Smith Chart...

https://imgur.com/9CA1Mzb

Is it due to some simulation parameters I don't define properly ?

Thanks

 

[dick_freebird]

OP says difference between simulation and fabrication, but
there's a third leg to that stool, which is measurement. That
holds the most potential for error and surprises, IMO.

I'd hope that there were on-same-die shorts and opens
de-embed structures for your VNA & probes, and that the
low-level layout of these matches the "access layout" for
the DUT.

The extreme behavior in the initial plots suggests a
resonant feature that a diode (oscillating types aside) ought
not to have. Could be time-of-flight in the harness and bad
termination, I dunno.

Diode DC bias and very small signal stimulus can show you
a capacitor or a resistor. Or something in between.

Large signal test stimulus can maybe bring on rectification
and multiplication / mixing. Might look at signal with a 'scope
to be sure that stimuli which "should" be ideal small signal,
are so when you put the whip to it. Like, sin(f) times cos(f)
can give you a 2f tone from only one source and its phase
shifts applied to a nonlinear (explicit, implicit, PIM...) element.
So is your diode put where it "should" be linear, or acting up?

For a realistic model fit you'd probably do some pulls at
varying DC bias, to get at those model params that emulate
bias dependent (depletion / injection) capacitance.

 

[Orey]

OP says difference between simulation and fabrication, but
there's a third leg to that stool, which is measurement. That
holds the most potential for error and surprises, IMO.

I'd hope that there were on-same-die shorts and opens
de-embed structures for your VNA & probes, and that the
low-level layout of these matches the "access layout" for
the DUT.

The extreme behavior in the initial plots suggests a
resonant feature that a diode (oscillating types aside) ought
not to have. Could be time-of-flight in the harness and bad
termination, I dunno.

Diode DC bias and very small signal stimulus can show you
a capacitor or a resistor. Or something in between.

Large signal test stimulus can maybe bring on rectification
and multiplication / mixing. Might look at signal with a 'scope
to be sure that stimuli which "should" be ideal small signal,
are so when you put the whip to it. Like, sin(f) times cos(f)
can give you a 2f tone from only one source and its phase
shifts applied to a nonlinear (explicit, implicit, PIM...) element.
So is your diode put where it "should" be linear, or acting up?

For a realistic model fit you'd probably do some pulls at
varying DC bias, to get at those model params that emulate
bias dependent (depletion / injection) capacitance.

I will do that. IF I understand clearly what you are saying, I should connect my VNA to an oscilloscope and look at the signal generated at one frequency (let say 2.45GHz). At this point, I should observe a sine signal.
I have already tried to connect a prototype to an other VNA and I observed the same reflection coefficient. At that time, I considered that the VNA wasn't the issue and it was more a simulation or fabrication issue.

Best

 

[Orey]

Hello,

I checked that I had the same results using an other calibrated VNA. I think that I can now conclude that the issue is due to fabrication. For a last check, I did some experiments with the diode and how I do my VIAs (1 mm diameter, with silver paste or copper strip with solder).

What is bothering me with below results is the experimental results seem coherent between them (not in case 3). Does it mean that I have a simulation issue? To check that I would like to kindly ask if someone can do the same simulation as me and send me the S11 data so I can close the doubt I still have over my simulation parameters. I use a FR4 substrate with Er=4.58 and TanDelta=0.022 @1MHz from datasheet (or Er=3.91 and TanDelta=0.0136 @2.449GHz with cavity characterization). The diode I use is SMS7621-5LF. And I used the package SOT23. All my simulation are done using an input power of -15 dBm.

One of the professor asked me to do more circuits since a PhD student had the same issue few years ago apparently until finding how he corrected the problem. Have you an idea of an other way to correct the problem?

Best

 

[volker@muehlhaus]

Your screenshots are always incomplete enough, and small enough, that we cannot exactly see what you did.
You can get much better help if upload the ADS workspace, so that we can see what you really did, including the testbench and more details.

 

[BigBoss]

I couldn't see "cond2" layer on your layout. Where is it ?
If you define an extra layer for GND connection, you have to lay it down underneath of the main layout.
Essentially , there is no sense at all to lay down an extra "cond2" layer but if you have already defined it, you have place it there.

 

[Orey]

Your screenshots are always incomplete enough, and small enough, that we cannot exactly see what you did.
You can get much better help if upload the ADS workspace, so that we can see what you really did, including the testbench and more details.

Here is my workspace.

EDIT: Seems like I cannot upload the file here, it doesn't appear. Please, find it on the following link: https://we.tl/t-9hfjoWWJJ1

 

[volker@muehlhaus]

I see no obvious mistakes. Mesh is fine and backside ground is modelled by boundary condition, which is fine.
The permittivity of 3.91 in your substrate definition is a bit unusual, typical FR4 would be 4.4 +/- 0.2, but if 3.91 is specified by your supplier you should use that value.

There are two missing files/libraries (Murata and HFDiode) so I could not simulate, but the EM part looks ok to me (except unusual permittivity).

 

[Orey]

I see no obvious mistakes. Mesh is fine and backside ground is modelled by boundary condition, which is fine.
The permittivity of 3.91 in your substrate definition is a bit unusual, typical FR4 would be 4.4 +/- 0.2, but if 3.91 is specified by your supplier you should use that value.

There are two missing files/libraries (Murata and HFDiode) so I could not simulate, but the EM part looks ok to me (except unusual permittivity).

View attachment 189942

The two libraries are not needed for the simulation. Can you also check how I define the ports of my EM simulation?

Thank you for your help!

 

[volker@muehlhaus]

Ok, I checked your simulation model and built another version with "my" settings.
You have a wide range of measurement results, which is THE measurement data to compare with for case 3?

You did not comment on permittivity, how accurate and trusted is the 3.91 value that you used?

 

[Orey]

We can compare it with the 3 experimental data. I made three circuits, one doing my via with silver paste, and the two others with copperstrip (but with more or less solder).

For the 3.91 permittivity, I trust this value at 80%. To be sure, I changed my simulation setting with the permittivity @1MHz and the frequency shift of the 2.5GHz peak is only 30MHz to the left.

I will do an other design with .5mm diameter for the VIA and silver paste, hoping that this way, the hole will be fully filled.

 

[volker@muehlhaus]

BTW, I just discovered one major mistake in your settings: you specified large signal simulation up to 6 GHz with 5 harmonics, but your EM model over covers DC to 6 GHz. That is why you see the warning regarding extrapolation.
For 5 harmonics you need EM data that goes up to 30 GHz, but then your port width isn't appropriate (not small compared to wavelength) and substrate thickness is multiple wavelength. Not sure what the best solution is, but your settings are not reliable as is.

--- Updated Apr 10, 2024 ---

Ok, I now increased EM frequency range to 20 GHz and used 3 harmonics (up to 3x6=18 GHz), so that should work.
Results have not changed much, the resonances stay where you had seen them before.

Given the massive differences between your measured data, e.g. no 2.45 GHz resonance at all with your blue measurement curve, I think you should create a layout with well defined via, measure and simulate that exact version, and see what differences remain.

You should also build a layout-only testcase to exclude any effect of the diode. For that, you could use the existing layout with the diode removed. That should be sensitive to substrate permittivity. I am very surprised why your model with diode shows so little change when going from 3.91 to 4.4, because that is already a big change in electrical length. But I see the same here when running the EM models, so it might be real.

 

[Orey]

Given the massive differences between your measured data, e.g. no 2.45 GHz resonance at all with your blue measurement curve, I think you should create a layout with well defined via, measure and simulate that exact version, and see what differences remain.

You should also build a layout-only testcase to exclude any effect of the diode. For that, you could use the existing layout with the diode removed. That should be sensitive to substrate permittivity. I am very surprised why your model with diode shows so little change when going from 3.91 to 4.4, because that is already a big change in electrical length. But I see the same here when running the EM models, so it might be real.

I don't know if I understood correctly what you mean't but is what I made in the 11th post of this thread (Jan 24th)? I made circuit without and with vias and looked at the impedance. As we can see on the results, there is a resistance ''offset" with the via. My interpretation: adding the diode that is non linear will rise the frequency offset even more.

 

[volker@muehlhaus]

I meant a PCB that uses the actual via size & shape as simulated, not the somewhat different wire as via replacement that you showed in the photo. The different measurements that you showed for layout 3 (two grounds) indicate that via details matter here. So if you don't measure what you have simulated, you have not built what you have simulated. Sounds trivial, but in my work in EM tool support that was the main issue many times.

Regarding the 3 cases with no gnd, one gnd and two grounds: that really changes how rectified DC current that can flow, so it is expected that results are different!? You need to decide which one is useful for your application case.

--- Updated Apr 10, 2024 ---

but is what I made in the 11th post of this thread (Jan 24th)?

Yes, I forgot that one without diode. Looks good.

--- Updated Apr 10, 2024 ---

but is what I made in the 11th post of this thread (Jan 24th)?

Yes, I forgot that one without diode. Looks good.

 

[Orey]

Regarding the 3 cases with no gnd, one gnd and two grounds: that really changes how rectified DC current that can flow, so it is expected that results are different!? You need to decide which one is useful for your application case.

In those 3 cases, I don't have any capacitor so there is no DC current that can flow (only parasitic capacitor due to the line/diode package). There shift are thus due to current flow to the ground?


Ok, I see. In terms of fabrication, I can only do via as i am doing actually. The diameter size and shape are the same as the one in simulation (1 mm diameter, circular).
In simulation, are the via simulated fully filled with conductor? If it's the case, this is the only difference I can see between the simulation and the PCB. I can try to reduce the diameter to .5 mm) hoping that the silver paste won't be fixed only on the side of the hole after being in the oven.

Does it sound good for you as an experiment test?

 

[volker@muehlhaus]

In those 3 cases, I don't have any capacitor so there is no DC current that can flow (only parasitic capacitor due to the line/diode package). There shift are thus due to current flow to the ground?

I missed that the diode configuration in your case has no obvious DC path, but now looked at the package parasitics. Please tweak your diode's parasitic CP from 80fF to 120fF, and you will see a large frequency shift for testcase 3. So that is really sensitive, and I wonder what tolerances apply there.