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If the supply rails are stiff then the latched "collector"
junctions will see full rail voltage - Vbe of the opposing
device in the SCR-pair.
If the rails are not able to sustain the latch current at
full voltage then they will sag toward a saturated region
of operation, down to Vbe+Vce(sat). Below this the SCR
may be triggered into conduction but unable to "latch"
regeneratively; below Vbe of the lesser-Vbe device there
will not be substantial current or current gain.
The role of the taps is to raise the SCR trigger current
above any possible D-B leakage, impact ionization,
substrate current injection level. This last is where max
input pin current specs are aimed.
Latch-up always starts in active region of involved transistors. If the supply rails are stiff enough to keep the transistors in active region during latch-up, the device will be most likely destroyed.
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