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Impact of scaling and power supply reduction in CMOS

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viggu007

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Hi all

Can anybody provide me an answer for the following question. I google searched for information on impact of scaling and power supply reduction ... but i am unable to get concrete results... can somebody suggest me a good book on CMOS. I have books of SM SZE,Ben G Streetman... is this sufficient ? pls guide me...

Question :

"Given that the power supply of CMOS digital circuits shrinks with each new generation,to maintain reasonable power densities and limit short channel effects. Write about the impact scaling (shrinking the power supply (VDD)) on the noise margins of CMOS digital circuits."


thank you ..
 

have a doubt in CMOS

Hi,

That book by Sze is very good. I think it would suffice. For better understanding you may reffer to Brennan. This is simple.

I can mail you some slides regarding this topic, on later date, as i'm not able to find them on my comp.

"enjoy your work"
 

have a doubt in CMOS

Pucknell .......did u try this book ?
 

Re: have a doubt in CMOS

i wud be glad to get the slides which you have mentioned..... i wud like to get an answer for the question that i mentioned..
 

Re: have a doubt in CMOS

Aouther name:Dan Clein
book name :CMOS IC LAYOUT
 

Re: have a doubt in CMOS

u follow the text book of MULLER and
a good book of donald neman
 

Re: have a doubt in CMOS

That's a nice book

You can also try this:

CMOS Digital IC -ANALYSIS and DESIGN
BY Sung Mo Kang
Yusuf Leblebici

tata Mcgrawhill Edition
 

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