If the highest metal of SRAM is top-2, can we use top or top-1 metal to route across SRAM macro?

[nemolee]

SRAM macro is generated by memory compiler.
If the highest metal of SRAM is top-2, can we use top or top-1 metal to route across SRAM macro ?
Is there any potential risk ?

 

[ThisIsNotSam]

typically, yes. it is a pretty common strategy to route over the macro for power distribution. but this changes from vendor to vendor. in the worst case, say your sram ends in M5 and you route some signal in M6 over it, you can get some vertical coupling. it is not a major concern.

 

[dick_freebird]

SRAM leaf cells are desired to be all Met1 (this may have
relaxed some, in the time of high interconnect stacks).
Row and column can be done in Met2 and maybe Met3
(have seen 64, 256K done in 2 layer metal).

Referring to the metal from top down, needs context
from the bottom up. "top-2" in a quad metal layer
flow might be hitting some macro internal routing
(or not) depending on leaf cell and array metal level
usage. In a 6-level interconnect, or higher, nothing
much to worry about; any device fields will be
dominated by the lower (met1, met2) plates and
field from above will terminate on these pretty much.

 

[navpics1]

Power routing & regular signal routing is fine.
Any clock route or critical signal route may need NDR or shielding for best practice