If I have 12 bits each 4 represent a number in binary, how do i convert it to binary?

[Elctgirl]

Hi,

How can I convert a 12 bit binary number where each 4 bits represent a character into an 8 bit binary number?

Example: 12 bit number : "001001000011" ==> 2,4,3 and I want to convert it to 243 ==> "11110011"

any help please?

What I did but still haven't reached a right answer:

---

Code VHDL - [expand]
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signal output1, output2, output3 : integer range 0 to 9;
signal output11, output22 : integer range 0 to 255;
 
begin
 
process(clk)
begin
if(clk'event and clk='1') then  
    case input(11 downto 8) is
 
        when  "0000" => output1 <= 0; 
        when  "0001" => output1 <= 1;
        when  "0010" => output1 <= 2;
        when  "0011" => output1 <= 3;
        when  "0100" => output1 <= 4;
        when  "0101" => output1 <= 5;
        when  "0110" => output1 <= 6;
        when  "0111" => output1 <= 7;
        when  "1000" => output1 <= 8;
        when  "1001" => output1 <= 9;
        when  others => output1 <= 0;
    end case;
    
    case input(7 downto 4) is
 
        when  "0000" => output2 <= 0; 
        when  "0001" => output2 <= 1;
        when  "0010" => output2 <= 2;
        when  "0011" => output2 <= 3;
        when  "0100" => output2 <= 4;
        when  "0101" => output2 <= 5;
        when  "0110" => output2 <= 6;
        when  "0111" => output2 <= 7;
        when  "1000" => output2 <= 8;
        when  "1001" => output2 <= 9;
        when  others => output2 <= 0;
    end case;
    
    case input(3 downto 0) is
 
        when  "0000" => output3 <= 0; 
        when  "0001" => output3 <= 1;
        when  "0010" => output3 <= 2;
        when  "0011" => output3 <= 3;
        when  "0100" => output3 <= 4;
        when  "0101" => output3 <= 5;
        when  "0110" => output3 <= 6;
        when  "0111" => output3 <= 7;
        when  "1000" => output3 <= 8;
        when  "1001" => output3 <= 9;
        when  others => output3 <= 0;
    end case;
end if;
end process;
 
output11 <= output1*100;
output22 <= output2*10;
finaloutput <= output1+output2+output3;
output<= std_logic_vector(to_unsigned(finaloutput,8));

---

 

[FvM]

What do you mean by "still haven't reached a right answer"? What are your requirements for a "right answer"?

Altough the BCD to binary operation can be described in less lines using ieee.numeric_std conversion functions, the shown code should basically work.

 

[Elctgirl]

Yes I know, I tried using the conversion function but it didn't work so I used the long conversion.

I don't have a specific criteria, It's just that after I use a test bench I don't get the correct answer.

 

[FvM]

It's just that after I use a test bench I don't get the correct answer.

But why? We need to see the complete entity and testbench to understand the reason.

 

[vipinlal]

you are looking for a BCD to binary converter. Try this code:

https://vhdlguru.blogspot.in/2015/04/vhdl-code-for-bcd-to-binary-conversion.html

 

[ads-ee]

The only issue I see with the OP's code is the range of output1 should be restricted to 0,1, or 2 as the range of the result for output11 can not be outside the range of 0 to 255. Perhaps the range restrictions are the root of the problem.

 

[FvM]

Perhaps the range restrictions are the root of the problem.

I don't think so. In synthesis, casting an integer to unsigned with insufficient length would just cause a wrap around respectively discarding of the upper two bits, e.g. 256 is output as zero.

A simulator stops with an error when the overflow occurs.