MayskiyJuk
Newbie level 5
Hi all. I'mtrying to start simulation of mixed-signal design using spectreVerilog. I created config view. While creating netlist I've got such errors:
All interface elements are from analogLib. Can anyone help me?
\o Delete psf data in /home/xxxxxx/simulation/TestMixed/spectreVerilog/config/psf.
\o generate netlist...
\o partition...
\o Statistics in creating analog/digital partitioning info for the design:
\o Sys Err: 0 Sys Warn: 0
\o Usr Err: 0 Usr Warn: 0
\o Fatal Sys Err: 0 Fatal Usr Err: 0
\o ...successful.
\o Begin MS Netlisting: Oct 15 12:56:04 2010
\o Begin IE Generation: Oct 15 12:56:04 2010
\o *USRWARN: You have used nondetailed Interface Element (IE) Generation
\o which will have less IE modeling accuracy than detailed IE Generation.
\o You should make sure that:
\o 1. All digital instance terminals connected at the same
\o Interface Net will have compatible logic and voltage thresholds.
\o 2. The loading and driving capabilities of all digital terminals
\o connected at the same Interface Net can be modeled with one IE
\o without significant loss of accuracy.
\o *USRERR: Net B, in module TestMixed, lib ADC_AdaptDriver, view schematic
\o requires the generation of Hierarchical Interface Element (IE) inside
\o a cellview having the view name that is a member of the analog
\o or digital stop view set. Such an IE will be ignored by the simulator.
\o Please change your design to avoid this limitation.
\o Unable to generate hierarchical interface elements for Network design (cell: TestMixed, lib: ADC_AdaptDriver, view: config)
\o Netlist Error: IE Generation-- Must correct Interface Element Generation errors before continuing with netlisting.
\o ...unsuccessful.
All interface elements are from analogLib. Can anyone help me?