Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

ICC timing report -from clock

Status
Not open for further replies.

muromir

Newbie level 2
Joined
Jun 19, 2013
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
17
Hello everyone,
I have a design with a few generated clock and some data paths between the different clock groups. When I try to report the timing between two clock groups with
report_timing -from Clk2 -to Clk1
I do not get some existing paths, no matter how many max_path and nworst I set. On the other hand, when I report the timing directly from the cells I am intersed in
report_timing -from I2/* -to Clk1
I see the path, but then the report shows me, that the launching cell is being clocked by a clock, called Clk2' (with an apostrophe after it) :
Startpoint: I2/Z_reg[7]
(rising edge-triggered flip-flop clocked by Clk2')

So my question is what exactly this apostrophe means, because apparently this has something to do with the behaviour of my report.

Best Regards
 

apostrophe measn clock source is fall edge. In other word , there are odd inverter function cells b/t source source and your launch ff's clock pin.

can you try report_timing -from [get_clocks Clk2] -to [get_clocks Clk1] , any path exported?


Phoeny
BR
 

Thanks for the answer. This is definitely the case - there is an inverter on the clock path. I did try to report with the get_clocks command as you suggested but the result is still the same. Apparently there is some other reason why this path is fragmented. Thank you anyways !
 

another possible reason for report_timing -from clock can't output timing path is that the slack is positive of path -from I2/* -to Clk1. report_timing -from Clk2 -to Clk1 -slack_less_than maybe help u. good luck



Thanks for the answer. This is definitely the case - there is an inverter on the clock path. I did try to report with the get_clocks command as you suggested but the result is still the same. Apparently there is some other reason why this path is fragmented. Thank you anyways !
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top