how to write a clock gating code with verilog?

[feel_on_on]

clock gating verilog

when synthesis with Design Compiler , how to write a clock gating code with verilog .then..........insert_clock_gating ,can synthesis a SNPS_CLOCK_GATE_HIGH....

 

[avimit]

verilog clock gating

you dont have to tweak or change your verilog code to insert Clock gates design compiler will automatically do it For you, provided your design/code gives dc an opportunity to do so
kr,
avi
http://www.vlsiip.com

 

[jarodz]

clock in verilog

When the output of FF feed back to his input, the sythesis tool can change insert the clock gating cell on the clock net to the pin of the FF.

Sincerely,
Jarod

 

[lordsathish]

clock gating in verilog

hi... could you explain me what exactly is clock gating...
as far as i know "the clock signal is fed to the modules in the design through gates which control the modules functioning"... and i also have heard that it is generally not advisable to use clock gating...why is it so...?

 

[calm]

snps_clock_gate_high

there are some kinds of examples of this issue, you can
find them in web.

 

[Wenf.Yeh]

clock gating code

here is a paper
hopes help!

 

[master_picengineer]

gated clock verilog

Thanks Wenf. Yeh !