How to watch the memory content at any stage of simulation?

[mpatel]

I implemented Block RAM from Xilinx IP CORE (size 16384 entires, 16 bit each). The question is how can I watch what is stored inside the memory at any stage of simulation?

 

[hys]

Re: Watch Memory content

You can use "Chipscope" from xilinx.... you need to determine before compilation what signal you want to be able to observe. Then you connect the memory signals to be observable. Then during runtime it is possible to observe them...

You need to read through the Chipscope manual...

Best Regards,
Harish
https://hdlplanet.tripod.com/
https://groups.yahoo.com/group/hdlplanet

 

[mpatel]

Re: Watch Memory content

You can use "Chipscope" from xilinx.... you need to determine before compilation what signal you want to be able to observe. Then you connect the memory signals to be observable. Then during runtime it is possible to observe them...

You need to read through the Chipscope manual...

Best Regards,
Harish
h**p://hdlplanet.tripod.com/
h**p://groups.yahoo.com/group/hdlplanet

Thanks hys,

But my question was different. I need to watch memory contect during simulation and not during hardware validation. I mean when I simulate a design, which has memory block, with ModelSim. I know the method where I can observe the output signals from memory but it gives opportunity to observe serially once at each clock cycle. I want to watch a complete memory, like what is stored at which address at once.

 

[VSMVDD]

Re: Watch Memory content

dont know about model sim
in proteus
you can capture a file or write a dll to capture a file just connect it to the memory unit

if its mcu based its down to the app

is there no capture device to watch the memory in there devices lists??

perhaps use some device to do you job accross the bus like a nvram chip this must have some sort of watch window
or model sim is shit still {havent looked at it since it was shit in 2000}

 

[Zeng Jie-jun]

Re: Watch Memory content

You can dump the memory database in verilog and then open and watch the content by debussy tool.

 

[aji_vlsi]

Re: Watch Memory content

Thanks hys,

But my question was different. I need to watch memory contect during simulation and not during hardware validation. I mean when I simulate a design, which has memory block, with ModelSim. I know the method where I can observe the output signals from memory but it gives opportunity to observe serially once at each clock cycle. I want to watch a complete memory, like what is stored at which address at once.

This is often called "Memory Viewer" in debug tools/simulators. In Modelsim, use: View -> Debug Windows -> Memory. VCS-DVE, Aldec's ACTIVE hdl all have this feature.

HTH
Ajeetha, CVC
https://www.systemverilog.us/ www.noveldv.com
* A Pragmatic Approach to VMM Adoption 0-9705394-9-5
* SystemVerilog Assertions Handbook, 0-9705394-7-9
* Using PSL/SUGAR